Accelerator architecture on a programmable platform

A method for operating an integrated circuit system, the method comprising:

• configuring programmable logic circuitry to provide first data to software-programmable vector processors, wherein the software-programmable vector processors are arranged in processing nodes in an interconnect structure, wherein each of the processing nodes is communicatively coupled to adjacent ones of the processing nodes via a router, wherein each of the processing nodes comprises one of the software-programmable vector processors, and wherein each of the software-programmable vector processors comprises processing elements;
• running an application on a hardware processor system;
• communicating the first data from the programmable logic circuitry to the software-programmable vector processors via a network-on-chip;
• loading the first data at the processing elements, wherein the processing elements comprise hardened circuits;
• processing the first data comprising integer and floating point data to generate processing data using the hardened circuits;
• and
• providing the processing data from the processing elements.

An adaptive acceleration platform, wherein the adaptive acceleration platform comprises:

• software-programmable vector processing circuitry comprising software-programmable vector processors arranged in processing nodes of an interconnect structure in an array, wherein each of the processing nodes is communicatively coupled to adjacent ones of the processing nodes in the array via a router, wherein each of the processing nodes comprises one of the software-programmable vector processors, wherein each of the software-programmable vector processors comprises processing elements, wherein each of the processing elements is capable of processing floating point data and integer data, and wherein the processing elements comprise hardened circuitry that is capable of executing instructions to generate processing data based on the instructions;
• and
• programmable logic circuitry, wherein the programmable logic circuitry is configurable to provide fourth data to the software-programmable vector processors using the interconnect structure;
• a hardware processor system;
• and
• a network-on-chip that communicatively couples the programmable logic circuitry, the software-programmable vector processing circuitry, and the hardware processor system.