Abstraction of UALink or NVLink Network-Attached Resources Including GPU HBM and HBF via CXL HDM-H and HDM-D Memory Regions

A system comprising:

• a host;
• a device coupled to the host via a Compute Express Link (CXL) link;
• and
• a first memory coupled to the device;
• wherein the device is configured to expose to the host a first memory region via a first CXL device type flow and a second memory region via a second CXL device type flow, wherein the first CXL device type flow is different from the second CXL device type flow;
• wherein the first memory region is associated with the first memory;
• wherein the second memory region is associated with a second memory accessible via an Ultra Accelerator Link (UALink) port of the device;
• and
• wherein the device is configured to translate between a protocol based on CXL and UALink Protocol Level Interface (UPLI) for requests targeting at least one of the first memory region or the second memory region.

A method comprising:

• exposing, by a device coupled to a host via a Compute Express Link (CXL) link, a first memory region via a first CXL device type flow and a second memory region via a second CXL device type flow, wherein the first CXL device type flow is different from the second CXL device type flow;
• wherein the first memory region is associated with a first memory;
• wherein the second memory region is associated with a second memory accessible via an NVLink-based protocol;
• and
• translating, by the device, between a protocol based on CXL and the NVLink-based protocol for at least one of the first memory region or the second memory region.

A system comprising:

• a host;
• a device coupled to the host via a Compute Express Link (CXL) link;
• and
• a first memory coupled to the device;
• wherein the device is configured to expose to the host a first memory region via a first CXL device type flow and a second memory region via a second CXL device type flow, wherein the first CXL device type flow is different from the second CXL device type flow;
• wherein the first memory region is associated with the first memory;
• wherein the second memory region is associated with a second memory accessible via an NVLink port of the device;
• and
• wherein the device is configured to translate between a protocol based on CXL and an NVLink-based protocol for requests targeting at least one of the first memory region or the second memory region.