Methods and apparatus for chip selecting techniques

An apparatus comprising:

• an input interface comprising a first signal path and a second signal path coupled to a memory controller;
• a controller configured to:
• receive, via the first signal path within a first time unit interval, a state signal indicating a memory selection operation;
• receive, via the first signal path within a second time unit interval consecutive to the first time unit interval, a first bit of a plurality of bits associated with the memory selection operation;
• receive, via the second signal path within the first time unit interval or the second time unit interval, a second bit of the plurality of bits;
• determine a memory selection configuration based on the plurality of bits comprising the first bit and the second bit.

A method comprising:

• determining a memory selection configuration represented by a plurality of bits to configure a memory device coupled via an interface comprising a first signal path and a second signal path;
• driving the first signal path, within a first time unit interval, to a state indicating a memory selection operation associated with the plurality of bits;
• driving the first signal path, within a second time unit interval consecutive to the first time unit interval, to an encoded state indicating a first bit of the plurality of bits;
• and
• driving the second signal path to an encoded state indicating a second bit of the plurality of bits within the first time unit interval or the second time unit interval.