Polymorphic system level cache
AssigneeQUALCOMM Incorporated
InventorsMahdi NAZM BOJNORDI, Paul Nicholas WHATMOUGH
Life of this patent
Estimating the term…
Abstract
Techniques described herein disclose a polymorphic system level cache. The polymorphic system level cache includes a cache controller configured to receive a memory request. The cache controller includes a plurality of registers, with each of the registers configured to generate an output based, at least in part, on the memory request. The output indicates whether an operation mode for a respective bank of the polymorphic system level cache is a cache operation mode or a non-cache operation mode.
Claims20
An apparatus, comprising:
- a plurality of processor units;
- a system level cache (SLC) communicatively coupled to each of the plurality of processing units and to a main memory that is separate from a system-on-chip (SoC) that includes the plurality of processing units;
- and
- a SLC controller configured to receive a memory request associated with the SLC, the SLC controller comprising a plurality of registers, each of the plurality of registers configured to generate an output based, at least in part, on the memory request, the output indicating whether an operation mode for a respective bank of the SLC is a cache operation mode or a non-cache operation mode,
- wherein each of the plurality of registers is configured to store:
- first data indicating whether the non-cache operation mode is disabled or enabled for the respective bank of the SLC;
- and
- second data indicating an address range for the respective bank of the SLC.
(canceled)
A method performed by a cache controller of a system level cache included on a system-on-chip, the method comprising:
- receiving a request to access the system level cache, the request including an address range corresponding to an address range for a respective bank of a plurality of banks of the system level cache;
- determining one of a cache operation mode or a non-cache operation mode as a selected operation mode for the respective bank;
- and
- accessing the respective bank of the system level cache according to the selected operation mode,
- wherein determining the selected operation mode of the respective bank comprises reading a value stored in a register communicatively coupled to the respective bank and indicative of the selected operation mode for the respective bank, and
- wherein the register is configured to store:
- first data indicating whether the non-cache operation mode is disabled or enabled for the respective bank of the system level cache;
- and
- second data indicating an address range for the respective bank of the system level cache.
(canceled)
(canceled)
Dependencies are inferred from the claim text.