Channel model implementation circuit, channel model implementation method, memory controller, electronic device and memory system

A memory controller, comprising:

• an error correction circuit, comprising;
• a channel model implementation circuit, comprising:
• at least one channel model implementation sub-circuit, comprising:
• a random number generation circuit, configured to:
• generate a random number;
• and
• a channel output information determination circuit configured to:
• receive one sub-data of channel input information;
• and determine channel output information corresponding to the sub-data, based on the random number, random number interval group information, and the sub-data;
• wherein the sub-data comprises at least two data states, and the random number interval group information comprises a mapping relationship between a plurality of random number intervals and a plurality of channel output information under different data states;
• an encoding circuit;
• and
• a decoding circuit;
• and
• a control unit configured to output original data,
• wherein the encoding circuit is configured to encode the original data to generate the channel input information, and the decoding circuit is configured to obtain decoded data based on a check matrix to be tested and the channel output information corresponding to each sub-data of the channel input information.

A method of channel model implementation, comprising:

• generating a random number;
• and
• determining channel output information corresponding to each sub-data of channel input information based on the random number, random number interval group information, and each sub-data of the channel input information,
• wherein the sub-data comprises at least two data states, and the random number interval group information comprises a mapping relationship between a plurality of random number intervals and a plurality of channel output information under different data states.