Error checking for machine learning hardware accelerators
OwnerPaul Ronald Barham, James Molloy +2inventors
InventorsPaul Ronald Barham, James Molloy, Sayed Hadi HashemI, Denys Vnukov
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OwnerPaul Ronald Barham, James Molloy +2inventors
InventorsPaul Ronald Barham, James Molloy, Sayed Hadi HashemI, Denys Vnukov
Estimating the term…
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting silent data corruptions (SDCs) or other errors induced by hardware faults that occur in hardware devices. One of the methods include receiving data representing a machine learning training workload for training a neural network; and executing the machine learning training workload across the plurality of hardware devices, the executing comprising, at each of at least a subset of the plurality of hardware devices, repeatedly performing training operations comprising: performing one or more computation operations to generate local output data at a corresponding time point; generating, based at least on the local output data, a first checksum for the corresponding time point for detecting errors induced by hardware faults; storing the first checksum in a memory; and transmitting the local output data from the hardware device to another hardware device over a network.
A method performed by a plurality of hardware devices, the method comprising:
A system comprising one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
A non-transitory computer storage medium encoded with instructions that, when executed by one or more computers, cause the one or more computers to perform operations comprising:
Dependencies are inferred from the claim text.