# US 2026/0219926 A1 · Dynamic memory power capping with criticality awareness

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- Number: US 2026/0219926 A1
- Document ID: US20260219926A1
- Status: Published application
- Kind: A1
- Application number: 19/428,968
- Filed: 2025-12-22
- Published: 2026-07-30
- Earliest claimed: 2016-09-19
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: Yasuko Eckert
- Web page: https://patentgrep.com/patent/US20260219926A1

## CPC

- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3225: of memory devices
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 3/0611: {in relation to response time}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0671: {In-line storage system}
- G06F 9/3009: {Thread control instructions}
- G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00)
- G06F 13/1626: {by reordering requests}
- G06F 13/1642: {with request queuing}
- G06F 2212/1028: Power efficiency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems, apparatuses, and methods for reducing memory power consumption without substantial performance impact by selectively delaying non-critical memory requests are disclosed. A system management unit transfers an amount of power allocated from a memory subsystem to other component(s) responsive to detecting a first condition. In one embodiment, the first condition is detecting one or more processors having tasks to execute. In response to the system management unit transferring the amount of power from the memory subsystem to one or more processors, a memory controller delays non-critical memory requests while performing critical memory requests to memory.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A memory controller comprising:
a pending queue configured to store memory requests classified as critical or non-critical; and
circuitry configured to convey an indication of a number of critical memory requests stored in the pending queue to a component external to the memory controller;
wherein the memory controller is further configured to prioritize service of the critical memory requests over the non-critical memory requests based at least in part on the indication.

### Claim 22 (depends on 21)

The memory controller of claim 21, wherein the component external to the memory controller comprises power allocation circuitry configured to reallocate power between a memory subsystem and one or more processors based at least in part on the indication.

### Claim 23 (depends on 21)

The memory controller of claim 21, wherein the indication of the number of critical memory requests is conveyed periodically while memory requests are pending in the pending queue.

### Claim 24 (depends on 21)

The memory controller of claim 21, wherein prioritizing service of the critical memory requests comprises dynamically adjusting a scheduling policy of the pending queue based on the indication.

### Claim 25 (depends on 21)

The memory controller of claim 21, wherein the memory controller is configured to adjust a threshold that governs servicing of non-critical memory requests based on the indication.

### Claim 26 (depends on 21)

The memory controller of claim 21, wherein the memory controller is configured to limit servicing of non-critical memory requests when the number of critical memory requests exceeds a predetermined value.

### Claim 27 (depends on 21)

The memory controller of claim 21, wherein the indication is conveyed to the external component to enable the external component to modify an operating condition of the memory controller.

### Claim 28

A method comprising:
storing, by circuitry, memory requests classified as critical or non-critical in a pending queue of a memory controller;
conveying an indication of a number of critical memory requests stored in the pending queue to a component external to the memory controller; and
prioritizing servicing of the critical memory requests over the non-critical memory requests based at least in part on the indication.

### Claim 29 (depends on 28)

The method of claim 28, wherein the component external to the memory controller comprises power allocation circuitry, and the method further comprises reallocating power between a memory subsystem and one or more processors based at least in part on the indication.

### Claim 30 (depends on 28)

The method of claim 28, wherein conveying the indication comprises periodically conveying the indication while memory requests are pending in the pending queue.

### Claim 31 (depends on 28)

The method of claim 28, wherein prioritizing service of the critical memory requests comprises dynamically adjusting a scheduling policy of the pending queue based on the indication.

### Claim 32 (depends on 28)

The method of claim 28, further comprising adjusting a threshold that governs servicing of non-critical memory requests based on the indication.

### Claim 33 (depends on 28)

The method of claim 28, further comprising limiting servicing of non-critical memory requests when the number of critical memory requests exceeds a predetermined value.

### Claim 34 (depends on 28)

The method of claim 28, further comprising enabling the external component to modify an operating condition of the memory controller based at least in part on the indication.

### Claim 35

A system comprising:
a memory subsystem;
one or more processors;
a memory controller comprising circuitry coupled to the memory subsystem and the one or more processors, the memory controller including a pending queue configured to store memory requests classified as critical or non-critical; and
a component external to the memory controller;
wherein the memory controller is configured to convey an indication of a number of critical memory requests stored in the pending queue to the external component and to prioritize service of the critical memory requests over the non-critical memory requests based at least in part on the indication.

### Claim 36 (depends on 35)

The system of claim 35, wherein the external component comprises power allocation circuitry configured to reallocate power between the memory subsystem and the one or more processors based at least in part on the indication.

### Claim 37 (depends on 35)

The system of claim 35, wherein the memory controller is configured to periodically convey the indication while memory requests are pending in the pending queue.

### Claim 38 (depends on 35)

The system of claim 35, wherein the memory controller is configured to dynamically adjust a scheduling policy of the pending queue based on the indication.

### Claim 39 (depends on 35)

The system of claim 35, wherein the memory controller is configured to adjust a threshold that governs servicing of non-critical memory requests based on the indication and to limit servicing of non-critical memory requests when the number of critical memory requests exceeds a predetermined value.

### Claim 40 (depends on 35)

The system of claim 35, wherein the external component is configured to modify an operating condition of the memory controller based at least in part on the indication.