Control method and controller for memory, and chip system

A chip system, comprising a target memory and a controller for the target memory, wherein the controller comprises:

• a slot control determination logic, configured to acquire slot configuration information for defining a slot control mode, the slot control mode indicating a switching mode between a working mode and a power-down mode in each control cycle of the target memory, wherein when only a slot unit in the slot configuration information is set to a fixed value, the slot control mode is a third control mode, and a command buffer has a first watermark, a first watermark timeout, a second watermark and a second watermark timeout, wherein the target memory is in the power-down mode when a number of access requests in the command buffer is less than the first watermark and a duration exceeds the first watermark timeout, and the target memory is in the working mode when the number of the access requests in the command buffer is greater than the second watermark and the duration exceeds the second watermark timeout, wherein the first watermark is less than the second watermark;
• the command buffer, configured to cache the access requests to the target memory in the power-down mode of the target memory;
• and
• a low-power control logic, configured to control the target memory according to the slot control mode, so that the target memory enters a low-power state in the power-down mode and processes the cached access requests to the target memory in the working mode.

A control method for a memory, comprising:

• acquiring slot configuration information for defining a slot control mode, the slot control mode indicating a switching mode between a working mode and a power-down mode in each control cycle of a target memory, wherein when only a slot unit in the slot configuration information is set to a fixed value, the slot control mode is a third control mode, and a command buffer has a first watermark, a first watermark timeout, a second watermark and a second watermark timeout, wherein the target memory is in the power-down mode when a number of access requests in the command buffer is less than the first watermark and a duration exceeds the first watermark timeout, and the target memory is in the working mode when the number of the access requests in the command buffer is greater than the second watermark and the duration exceeds the second watermark timeout, wherein the first watermark is less than the second watermark;
• caching the access requests to the target memory in the power-down mode of the target memory using the command buffer;
• and
• controlling the target memory according to the slot control mode, so that the target memory enters a low-power state in the power-down mode and processes the cached access requests to the target memory in the working mode.