Resistive random-access memory (rram) based in memory computing for efficient implementation of gated recurrent units

A system comprising:

• a memory storing instructions;
• one or more communication interfaces;
• an In-Memory Computing (IMC) controller unit;
• and
• one or more hardware processors coupled to the memory and the IMC controller via the one or more communication interfaces, wherein the one or more hardware processors are configured by the instructions to:
• map a specific GRU weight network parameter from a plurality of GRU weight network parameter to each of a memristor array structure of a Resistive Random-Access Memory In-Memory Computing-based gated recurrent unit (RRAM IMC-based GRU) network architecture in a skewed arrangement for being stored, wherein the RRAM IMC-based GRU network architecture comprises a first storage unit, a second storage unit, an In Memory Computing (IMC) controller unit, and a reduced instruction set computing (RISC-V) based core processing unit, wherein the second storge unit comprises a plurality of modules that includes a first set of IMC circuit modules, a second set of IMC circuit modules, an output specific IMC circuit module, an adder circuit module, and one or more biasing circuit modules, and wherein each IMC circuit module in the first set of IMC circuit modules and the second set of IMC circuit modules comprise a plurality of RRAM devices that are arranged as a plurality of memristor array structures, wherein each memristor array structure from the plurality of memristor array structures comprises a plurality of rows and a plurality of columns connected by a plurality of memristive cells, and wherein each GRU weight network parameter represents a conductance value;
• input a multi-bit input vector to a plurality of rows of a first memristor array structure of the first set of IMC circuit modules that is mapped to a specific GRU weight network parameter and a past hidden state vector to the plurality of rows of a first memristor array structure of the second set of IMC circuit modules that is mapped to the corresponding specific GRU weight network parameter, wherein the multi-bit input vector and the past hidden state vector represent a voltage value;
• concurrently perform a plurality of GRU operations on the RRAM IMC-based GRU network architecture using the multi-bit input vector, the plurality GRU weight network parameters, and the past hidden state vector for obtaining a plurality of IMC output values, wherein the plurality of GRU operations are concurrently performed till an end of the multi-bit input vector application and a last value of the past hidden state vector is applied to the RRAM IMC-based GRU network architecture, and wherein the plurality of GRU operations comprise at least one of (i) a multiply-accumulate (MAC) operation, (ii) an addition, (iii) a computation of one or more activation functions, and (iii) a computation of Hadamard products of the one or more activation functions and a corresponding output of a past GRU operation from the plurality of GRU operations, and wherein the in memory computing IMC output represents an accumulated bitline current value;
• determine a digital value corresponding to each of the plurality of IMC output values using an analog-to-Digital Converter (ADC);
• and
• determine a final output value for each of the plurality of IMC output values based on accumulation of the digital value corresponding to each of the plurality of IMC output values with one or more bias input values provided by the one or more biasing circuit modules using the adder circuit module.

One or more non-transitory machine-readable information storage mediums comprising one or more instructions which when executed by one or more hardware processors cause:

• mapping a specific GRU weight network parameter from a plurality of GRU weight network parameter to each of a memristor array structure of a Resistive Random-Access Memory In-Memory Computing-based gated recurrent unit (RRAM IMC-based GRU) network architecture in a skewed arrangement for being stored, wherein the RRAM IMC-based GRU network architecture comprises a first storage unit, a second storage unit, an In Memory Computing (IMC) controller unit, and a reduced instruction set computing (RISC-V) based core processing unit, wherein the second storge unit comprises a plurality of modules that includes a first set of IMC circuit modules, a second set of IMC circuit modules, an output specific IMC circuit module, an adder circuit module, and one or more biasing circuit modules, and wherein each IMC circuit module in the first set of IMC circuit modules and the second set of IMC circuit modules comprise a plurality of RRAM devices that are arranged as a plurality of memristor array structures, wherein each memristor array structure from the plurality of memristor array structures comprises a plurality of rows and a plurality of columns connected by a plurality of memristive cells, and wherein each GRU weight network parameter represents a conductance value;
• inputting a multi-bit input vector to a plurality of rows of a first memristor array structure of the first set of IMC circuit modules that is mapped to a specific GRU weight network parameter and a past hidden state vector to the plurality of rows of a first memristor array structure of the second set of IMC circuit modules that is mapped to the corresponding specific GRU weight network parameter, wherein the multi-bit input vector and the past hidden state vector represent a voltage value;
• concurrently performing a plurality of GRU operations on the RRAM IMC-based GRU network architecture using the multi-bit input vector, the plurality GRU weight network parameters, and the past hidden state vector for obtaining a plurality of IMC output values, wherein the plurality of GRU operations are concurrently performed till an end of the multi-bit input vector application and a last value of the past hidden state vector is applied to the RRAM IMC-based GRU network architecture, and wherein the plurality of GRU operations comprise at least one of (i) a multiply-accumulate (MAC) operation, (ii) an addition, (iii) a computation of one or more activation functions, and (iii) a computation of Hadamard products of the one or more activation functions and a corresponding output of a past GRU operation from the plurality of GRU operations, and wherein the in memory computing IMC output represents an accumulated bitline current value;
• determining a digital value corresponding to each of the plurality of IMC output values using an analog-to-Digital Converter (ADC);
• and
• determining a final output value for each of the plurality of IMC output values based on accumulation of the digital value corresponding to each of the plurality of IMC output values with one or more bias input values provided by the one or more biasing circuit modules using the adder circuit module.