Distributed computing in a package with dram dies and a logic die

A device, comprising:

• a first die comprising:
• a plurality of Through-Silicon Vias (TSVs) distributed in a plurality of areas of the first die,
• a first compute component,
• a second compute component,
• a first set of TSVs associated with the first compute component and connecting stacked dies of the device, wherein the first set of TSVs comprises one or more of the plurality of TSVs in a first area of the first die, and
• a second set of TSVs associated with the second compute component and connecting the stacked dies of the device, wherein the second set of TSVs comprises one or more of the plurality of TSVs in a second area of the first die different from the first area;
• and
• a second die, stacked on the first die, comprising:
• a first memory bank module connected to the first compute component using the first set of TSVs, and
• a second memory bank module connected to the second compute component using the second set of TSVs.

A system, comprising:

• an accelerator processor configured for performing a compute function, the accelerator processor comprising:
• a first die, comprising:
• a first compute component,
• a second compute component,
• a first set of Through Silicon Vias (TSVs) associated with the first compute component and connecting stacked dies of the device, and
• a second set of TSVs associated with the second compute component and connecting the stacked dies of the device;
• and
• a second die, stacked on the first die, comprising:
• a first memory bank module connected to the first compute component using the first set of TSVs, and
• a second memory bank module connected to the second compute component using the second set of TSVs;
• and
• a memory storing instructions, the instructions to be executed by the accelerator processor to perform the compute function.