Built-in synchronizer clock gating for low power consumption

A digital circuit having multiple digital systems, comprising:

• a first digital system, operating in a first domain;
• a second digital system, operating in a second domain;
• and
• a synchronizer, coupled to the first and second digital systems for synchronizing data transfer operations across a domain boundary between the first and second domains, generating a synchronous output signal for the second digital system from an asynchronous input signal receiving from the first digital system, wherein the synchronizer comprises:
• a clock gating logic, for receiving the asynchronous input signal, the synchronous output signal, and a clock signal, and adaptively gating the clock signal according to the asynchronous input signal and the synchronous output signal;
• and
• a synchronizer flop bank comprising a number of synchronization flip flops, for receiving the asynchronous input signal and the clock signal to generate the synchronous output signal, wherein the clock signal is adaptively gated by the clock gating logic.