Array substrate, display panel and display apparatus

An array substrate, comprising:

• a first base substrate, comprising a plurality of sub-pixel areas arrayed along a first direction and a second direction and a wiring area between adjacent sub-pixel areas;
• wherein the first direction intersects with the second direction;
• a plurality of thin-film transistors, disposed on one side of the first base substrate in the wiring area;
• wherein each of the plurality of thin-film transistors comprises a first pole, a second pole and a third pole;
• a first electrode, disposed on one side of the first pole back from the first base substrate, wherein the first electrode comprises a plurality of first opening areas;
• wherein an orthographic projection of the first opening areas on the first base substrate falls within the wiring area, and the orthographic projection of the first opening areas on the first base substrate overlaps with an orthographic projection of the first pole on the first base substrate;
• a plurality of second electrodes, disposed on the same side of the first base substrate as the first electrode;
• wherein each of the plurality of second electrodes comprises a first connection portion;
• the first connection portion comprises a first sub-connection portion electrically connected to the first pole and a second sub-connection portion electrically connected to the first sub-connection portion;
• the second sub-connection portion comprises structures respectively located on opposite sides of the first connection portion;
• an orthographic projection of the first sub-connection portion on the first base substrate falls within the orthographic projection of the first opening areas on the first base substrate, and an orthographic projection of the second sub-connection portion on the first base substrate overlaps with the orthographic projection of the first pole on the first base substrate and the orthographic projection of the first opening areas on the first base substrate.

A display panel, comprising:

• an array substrate;
• wherein the array substrate comprises a plurality of data lines;
• an opposite substrate, disposed opposite the array substrate, comprising a second base substrate, and a plurality of spacers disposed on one side of the second base substrate toward a liquid crystal layer;
• an orthographic projection of the spacers on the first base substrate falls within the wiring area, and the orthographic projection of the spacers on the first base substrate overlaps with an orthographic projection of the data lines on the first base substrate;
• the liquid crystal layer, between the array substrate and the opposite substrate;
• wherein the array substrate further comprises:
• a first base substrate, comprising a plurality of sub-pixel areas arrayed along a first direction and a second direction and a wiring area between adjacent sub-pixel areas;
• wherein the first direction intersects with the second direction;
• a plurality of thin-film transistors, disposed on one side of the first base substrate in the wiring area;
• wherein each of the plurality of thin-film transistors comprises a first pole, a second pole and a third pole;
• a first electrode, disposed on one side of the first pole back from the first base substrate, and comprising a plurality of first opening areas;
• wherein an orthographic projection of the first opening areas on the first base substrate falls within the wiring area, and the orthographic projection of the first opening areas on the first base substrate overlaps with an orthographic projection of the first pole on the first base substrate;
• a plurality of second electrodes, disposed on the same side of the first base substrate as the first electrode;
• wherein each of the plurality of second electrodes comprises a first connection portion;
• the first connection portion comprises a first sub-connection portion electrically connected to the first pole and a second sub-connection portion electrically connected to the first sub-connection portion;
• the second sub-connection portion comprises structures respectively located on opposite sides of the first connection portion;
• an orthographic projection of the first sub-connection portion on the first base substrate falls within the orthographic projection of the first opening areas on the first base substrate, and an orthographic projection of the second sub-connection portion on the first base substrate overlaps with the orthographic projection of the first pole on the first base substrate and the orthographic projection of the first opening areas on the first base substrate.