US 2026/0215345 A1 · SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first surface and a second surface opposite thereto, a first through via penetrating the first semiconductor substrate and extending from the first surface to the second surface of the first semiconductor substrate, a first copper alloy seed layer positioned on a side surface of the first through via, a first lower wiring structure positioned on the first surface of the first semiconductor substrate and including a first lower pad, and a first upper wiring structure positioned on the second surface of the first semiconductor substrate and including a first upper pad; and a second semiconductor chip positioned on the first semiconductor chip, wherein a weight ratio of copper included in the first lower pad is higher than a weight ratio of copper included in the first through via.

Claims20

Dependent claims

A semiconductor package comprising:

a first semiconductor chip comprising:
a first semiconductor substrate including a first surface and a second surface opposing one another,
a first through via extending in the first semiconductor substrate from the first surface of the first semiconductor substrate to the second surface of the first semiconductor substrate,
a first copper alloy seed layer on a side surface of the first through via,
a first lower wiring structure on the first surface of the first semiconductor substrate and including a first lower pad, and
a first upper wiring structure on the second surface of the first semiconductor substrate and including a first upper pad;
and
a second semiconductor chip on the first semiconductor chip,
wherein the first lower pad and the first through via each comprise copper, and
wherein a weight ratio of copper in the first lower pad is greater than a weight ratio of copper in the first through via.

7 more elements

A semiconductor package comprising:

a first semiconductor chip comprising:
a first semiconductor substrate including a first surface and a second surface opposing one another,
a first through via extending in the first semiconductor substrate from the first surface of the first semiconductor substrate to the second surface of the first semiconductor substrate,
a first copper alloy seed layer on a side surface of the first through via,
a first lower wiring structure on the first surface of the first semiconductor substrate, wherein the first lower wiring structure includes a first lower pad and a first lower copper seed layer on a side surface of the first lower pad, and
a first upper wiring structure on the second surface of the first semiconductor substrate, wherein the first upper wiring structure includes a first upper pad and a first upper copper seed layer on a side surface of the first upper pad;
a second semiconductor chip on the first semiconductor chip and comprising:
a second semiconductor substrate including a first surface and a second surface opposing one another,
a second through via extending in the second semiconductor substrate from the first surface of the second semiconductor substrate to the second surface of the second semiconductor substrate,
a second copper alloy seed layer on a side surface of the second through via,
a second lower wiring structure on the first surface of the second semiconductor substrate, wherein the second lower wiring structure includes a second lower pad and a second lower copper seed layer on a side surface of the second lower pad, and
a second upper wiring structure on the second surface of the second semiconductor substrate, wherein the second upper wiring structure includes a second upper pad and a second upper copper seed layer on a side surface of the second upper pad;
and
a molding layer on the first semiconductor chip and in contact with a side surface of the second semiconductor chip,
wherein each of the first copper alloy seed layer, the first through via, the second copper alloy seed layer, and the second through via comprises copper and a first metal other than copper,
wherein a weight ratio of the first metal in the first through via is less than a weight ratio of the first metal in the first copper alloy seed layer, and
wherein a weight ratio of the first metal in the second through via is less than a weight ratio of the first metal in the second copper alloy seed layer.

14 more elements

Dependencies are inferred from the claim text.

Semiconductor package

Life of this patent

Semiconductor package

Life of this patent

Abstract

Claims20