Semiconductor Package with Side Wall Interconnection
AssigneeAvago Technologies International Sales Pte. Limited
InventorsSam Karikalan, Sam Zhao, Mayank Mayukh, Liming Tsau, Dharmendra Saraswat, Arun Ramakrishnan, Reza Sharifi
Life of this patent
Estimating the term…
Abstract
Tools and techniques for a semiconductor package providing side wall interconnections are provided. An apparatus includes two or more die layers that are bonded together, the first 3D stacked die package comprising a top surface, bottom surface, and one or more side walls. A first side wall of the one or more side walls includes two or more side wall pads, wherein each side wall pad of the two or more side wall pads is coupled to an interconnect of a respective die layer of the two or more die layers.
Claims20
An apparatus comprising:
- two or more die layers that are bonded together, the two or more die layers comprising a top surface, bottom surface, and one or more side walls
- wherein a first side wall of the one or more side walls comprises two or more side wall bumps, wherein each side wall bump of the two or more side wall bumps is coupled to an interconnect of a die layer of the two or more die layers, and
- an interconnection layer coupled to the first side wall, the interconnection layer comprising a plurality of micro bumps arranged in an array, the interconnection layer configured to electrically couple the two or more side wall bumps to the plurality of micro bumps.
A semiconductor device comprising:
- a three-dimensional (3D) stacked die package comprising two or more die layers bonded together, the 3D stacked die package having a top surface, a bottom surface, and a plurality of side walls;
- a plurality of side wall pads disposed on a first side wall of the plurality of side walls, each side wall pad of the plurality of side wall pads coupled to an interconnect of a respective die layer of the two or more die layers;
- and
- an interconnection layer disposed on the first side wall, the interconnection layer comprising an array of bumps configured to provide electrical connectivity to the plurality of side wall pads.
A semiconductor device comprising:
- a 3D stacked die package comprising two or more die layers bonded via oxide-oxide bonding or hybrid bonding;
- a plurality of side wall pads arranged at a side wall of the 3D stacked die package, the plurality of side wall pads comprising exposed through-silicon vias (TSVs);
- a redistribution layer (RDL) disposed on the side wall and coupled to the plurality of side wall pads;
- and
- an interconnection layer disposed on the RDL, the interconnection layer comprising an array of bumps.
Dependencies are inferred from the claim text.