Semiconductor package having a die pad, a semiconductor transistor die and a layer structure having a ceramic layer
AssigneeInfineon Technologies Austria AG
InventorsEdward Fürgut, Thai Kee Gan, Robert Rõsner
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a leadframe having a die pad and a plurality of leads. The die pad has a first main face and a second main face opposite to the first main face. A semiconductor transistor die is disposed on the first main face of the die pad. A layer structure is disposed on the second main face of the die pad. The layer structure includes a ceramic layer. An encapsulant embeds the die pad, inner portions of the leads, the semiconductor transistor die, and the layer structure. At least a portion of an uppermost layer of the layer structure is exposed to the outside.
Claims18
A semiconductor package, comprising:
- a leadframe comprising a die pad and a plurality of leads, the die pad comprising a first main face and a second main face opposite to the first main face;
- a semiconductor transistor die on the first main face of the die pad;
- a layer structure on the second main face of the die pad, the layer structure comprising a ceramic layer;
- and
- an encapsulant embedding the die pad, inner portions of the leads, the semiconductor transistor die, and the layer structure,
- wherein at least a portion of an uppermost layer of the layer structure is exposed to the outside.
A method of manufacturing a semiconductor package, the method comprising:
- providing a leadframe comprising a die pad and a plurality of leads, the die pad comprising a first main face and a second main face opposite to the first main face;
- attaching a semiconductor transistor die to the first main face of the die pad;
- attaching a layer structure to the second main face of the die pad, the layer structure comprising one of a direct copper bond, a direct aluminum bond, an active metal braze, or an insulated metal substrate;
- and
- applying an encapsulant to embed the die pad, inner portions of the leads, the semiconductor transistor die, and the layer structure, so that at least a portion of an uppermost layer of the layer structure is exposed to the outside.
Dependencies are inferred from the claim text.