Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a first active region on a substrate;
• a first channel pattern and a second channel pattern on the first active region, each of the first channel pattern and second channel pattern comprising a plurality of semiconductor patterns wherein the plurality of semiconductor patterns are vertically stacked with respect to the substrate and are spaced apart from each other;
• a first gate pattern crossing the first channel pattern;
• a second gate pattern crossing the second channel pattern;
• and
• an insertion pattern between the substrate and a lowermost semiconductor pattern of the plurality of semiconductor patterns of the second channel pattern,
• wherein a number of inner electrodes of the first gate pattern is greater than a number of inner electrodes of the second gate pattern, and
• wherein a bottom surface of the second gate pattern is at a vertical level that is lower, with respect to the substrate, than a vertical level of a top surface of the insertion pattern.

A semiconductor device, comprising:

• a first active region including a first region and a second region, on a substrate;
• a first channel pattern on the first region and a second channel pattern on the second region, each of the first channel pattern and the second channel pattern comprising a plurality of semiconductor patterns wherein the plurality of semiconductor patterns are vertically stacked with respect to the substrate and are spaced apart from each other;
• a source/drain pattern on the first active region;
• an active contact on a top surface of the source/drain pattern;
• a first gate pattern crossing the first channel pattern, the first gate pattern comprising inner electrodes interposed between the plurality of semiconductor patterns of the first channel pattern and between the first channel pattern and the substrate;
• a second gate pattern crossing the second channel pattern, the second gate pattern comprising inner electrodes positioned between the plurality of semiconductor patterns of the second channel pattern;
• a gate contact on a top surface of the second gate pattern;
• and
• an insertion pattern between the substrate and a lowermost semiconductor pattern of the plurality of semiconductor patterns of the second channel pattern,
• wherein a number of the inner electrodes of the first gate pattern is greater than a number of the inner electrodes of the second gate pattern, and
• wherein the second gate pattern covers a side surface of the insertion pattern.