Sacrificial stressors for applying stress to channel regions

A method comprising:

• forming a first plurality of sacrificial layers between a first plurality of semiconductor nanostructures in first formation processes;
• forming a second plurality of sacrificial layers between a second plurality of semiconductor nanostructures in second formation processes, wherein the first formation processes are separate processes from the second formation processes;
• forming first source/drain regions on opposing sides of the first plurality of semiconductor nanostructures;
• forming second source/drain regions on opposing sides of the second plurality of semiconductor nanostructures;
• in a same etching process, removing the first plurality of sacrificial layers and the second plurality of sacrificial layers to form first recesses and second recesses, respectively, wherein the first plurality of sacrificial layers comprise a different material than the second plurality of sacrificial layers;
• forming a first gate stack filling the first recesses;
• and
• forming a second gate stack filling the second recesses.

A method comprising:

• forming a first transistor comprising:
• forming first semiconductor nanostructure over a semiconductor substrate, wherein the first semiconductor nanostructure has a first internal stress;
• forming a first source region and a first drain region on opposing sides of, and joined to, the first semiconductor nanostructure, wherein the first source region and the first drain region have a second internal stress smaller than the first internal stress;
• and
• forming a first gate stack, wherein the first gate stack comprises a first portion, and wherein in a first cross-section of the first semiconductor nanostructure, the first portion of the first gate stack fully encircles the first semiconductor nanostructure, and wherein the first portion of the first gate stack has a third internal stress smaller than the first internal stress.