Memory device having three-dimensional structure and method of operating the same

A memory device comprising:

• a peripheral circuit structure;
• and
• a cell array structure on the peripheral circuit structure,
• wherein the cell array structure comprises:
• gate electrodes spaced apart in a vertical direction;
• a storage structure passing through the gate electrodes, wherein the storage structure comprises a charge storage film and is in a vertical opening extending in the vertical direction;
• a channel layer on an inner wall of the storage structure in the vertical opening, the channel layer comprising an oxide semiconductor;
• a conductive interfacial layer on an inner wall of the channel layer in the vertical opening;
• a back-side electrode layer on an inner wall of the conductive interfacial layer in the vertical opening;
• and
• a bit line pad connected to a bottom portion of the channel layer in the vertical opening and spaced apart from the back-side electrode layer in the vertical direction.

A memory device comprising:

• a peripheral circuit structure;
• and
• a cell array structure on the peripheral circuit structure,
• wherein the cell array structure comprises:
• gate electrodes spaced apart in a vertical direction;
• a storage structure passing through the gate electrodes, wherein the storage structure comprises a charge storage film and is in a vertical opening extending in the vertical direction;
• a channel layer on an inner wall of the storage structure in the vertical opening, the channel layer comprising an oxide semiconductor;
• a conductive interfacial layer on an inner wall of the channel layer in the vertical opening;
• a back-side electrode layer on an inner wall of the conductive interfacial layer in the vertical opening;
• a bit line pad connected to a bottom portion of the channel layer in the vertical opening and spaced apart from the back-side electrode layer in the vertical direction;
• a spacer insulating layer on the inner wall of the channel layer in the vertical opening, wherein the spacer insulating layer is between the back-side electrode layer and the bit line pad and is between the conductive interfacial layer and the bit line pad;
• a bit line connected to the bit line pad;
• a common source line on an outer wall of an upper portion of the channel layer;
• a first connection via connected to the common source line;
• and
• a second connection via connected to the back-side electrode layer.