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US 2026/0214894 A1Published application
Non-volatile memory integrated circuit and corresponding manufacturing method
AssigneeSTMicroelectronics International N.V.
InventorsMichele Calvo, Stephan Niel, Francesco La Rosa
Life of this patent
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Abstract
The non-volatile memory integrated circuit comprises memory cells including a state transistor having a control gate, a floating gate, and an erase gate, and a transistor for selecting a vertical gate buried in a semiconductor substrate.
Claims20
A non-volatile memory integrated circuit, comprising:
- two memory cells, each of the two memory cells including a state transistor having a control gate and a floating gate so that the two memory cells comprises two state transistors with two control gates and two floating gates, the two memory cells comprising a erase gate and a select transistor, the select transistor comprising a vertical gate buried in the semiconductor substrate,
- the select transistor being common to the state transistors arranged on either side of the vertical gate, and
- the erase gate being common to the two state transistors arranged on either side of the erase gate.
A method for manufacturing a non-volatile memory integrated circuit including at least two memory cells, the method comprising:
- forming a vertical gate select transistor buried in a semiconductor substrate, the select transistor comprising a vertical gate;
- forming a first state transistor for a first of the memory cells and a second state transistor for a second of the memory cells, each of the first and second state transistors having a control gate and a floating gate, the select transistor being common to the first and second state transistors arranged on either side of the vertical gate;
- and
- forming an erase gate of the first and second state transistors, the erase gate being common to the first and second state transistors arranged on either side of the erase gate.
1 more element
A method for manufacturing a non-volatile memory integrated circuit including at least two memory cells, the method comprising:
- forming a vertical gate select transistor buried in a semiconductor substrate, the select transistor comprising a vertical gate;
- forming a first state transistor for a first of the memory cells and a second state transistor for a second of the memory cells, each of the first and second state transistors having a control gate and a floating gate, the select transistor being common to the first and second state transistors arranged on either side of the vertical gate;
- and
- forming an erase gate of the first and second state transistors, the erase gate being common to the first and second state transistors arranged on either side of the erase gate, wherein the memory cells are arranged in a memory plane;
- forming bit lines traversing the memory plane in a first direction, the bit lines coupled to drain regions of the first and second state transistors;
- forming control gate lines comprising the control gates of the first and second state transistors;
- forming an erase line comprising the erase gate of the first and second state transistors;
- and
- forming word lines traversing the memory plane in a second direction, the word lines comprising the vertical gates of the select transistors.
6 more elements
Dependencies are inferred from the claim text.