Memory device using semiconductor element

A memory device using a semiconductor element,

• wherein a plurality of semiconductor memory cells including a first memory cell and a second memory cell are arranged on a substrate,
• the first memory cell includes
• a first semiconductor base extending in a first direction parallel to the substrate,
• the second memory cell includes
• a second semiconductor base separated from the first semiconductor base in a vertical direction or a horizontal direction, the second semiconductor base overlapping the first semiconductor base in plan view when the second semiconductor base is separated from the first semiconductor base in the vertical direction, the second semiconductor base being at a position overlapping the first semiconductor base in sectional view when the second semiconductor base is separated from the first semiconductor base in the horizontal direction,
• wherein the memory device includes
• a first impurity region and a second impurity region respectively continuous with one end and another end of the first semiconductor base,
• a third impurity region and a fourth impurity region respectively continuous with one end and another end of the second semiconductor base,
• a first gate insulating layer in contact with a first side surface out of side surfaces of the first semiconductor base facing the second semiconductor base,
• a second gate insulating layer in contact with a second side surface out of side surfaces of the second semiconductor base facing the first semiconductor base, and
• one or two first gate conductor layers and one or two second gate conductor layers, each of the first gate conductor layers and each of the second gate conductor layers being in contact with the first and second gate insulating layers so as to function as the gate conductor layers common to the first memory cell and second memory cell, the first gate conductor layers and the second gate conductor layers being arranged in the first direction and isolated from each other,
• wherein, the first to fourth impurity regions and the first and second gate conductor layers are configured such that, when the memory device is controlled so as to apply a voltage to the first to fourth impurity regions and the first and second gate conductor layers,
• a data write operation that, in one or both of the first semiconductor base and the second semiconductor base, causes a part or an entirety of a positive hole group or an electron group serving as a majority carrier to remain in one or both of the first semiconductor base and the second semiconductor base,
• a data write-protect operation that, during the data write operation, prohibits remaining of the part or the entirety of the positive hole group or the electron group in another or both of the first semiconductor base and the second semiconductor base,
• a data erase operation that discharges the remaining positive hole group or the remaining electron group from one or both of the first and second impurity regions and one or both of the third and fourth impurity regions, and
• a data read operation causing, by using storage data of a data write state or a data erase state in one of the first semiconductor base and the second semiconductor base, a current to flow through the first semiconductor base or the second semiconductor base or prohibiting flowing of the current through the first semiconductor base or the second semiconductor base are performed, and
• wherein the second impurity region is connected to a first bit line, the fourth impurity region is connected to a second bit line, and the first and third impurity regions are connected to a source line.