Reducing cross-talk among signals
AssigneeShaoxing Yuanfang Semiconductor Co., Ltd.
InventorsMadhusudan Srinivasan, Raja Prabhu J, Harshit Rathore, Laxmi Choudhary, Kranthi Kadiyala
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Abstract
A circuit contains multiple signal traces, multiple transmitters and multiple receivers. Each of the multiple signal traces has an input end and an output end, and propagates a corresponding input signal received at its input end to its output end. Each of the multiple transmitters is connected to a corresponding input end of a respective signal trace. Each of the multiple receivers is connected to a corresponding output end of a respective signal trace. Each receiver contains a self-biased inverter biased in a high-gain region. The DC operating-point of each driver equals that of the corresponding receiver.
Claims20
A circuit comprising:
- a plurality of signal traces, each signal trace having a corresponding input end and a corresponding output end, each signal trace to propagate a corresponding signal received at the corresponding input end to the corresponding output end;
- a plurality of transmitters, with an output of each transmitter being coupled to a corresponding input end of a respective signal trace;
- and
- a plurality of receivers, with an input of each receiver being coupled to a corresponding output end of a respective signal trace,
- wherein each receiver comprises a self-biased inverter biased in a high-gain region,
- wherein a DC operating-point of each transmitter equals that of the corresponding receiver.
A system comprising:
- a plurality of processors for executing instructions;
- a plurality of memory units for storing instructions and data;
- an interconnect to couple said processors to said memory units;
- and
- a clock integrated circuit (IC) to generate a plurality of clock signals, wherein a respective clock signal of said plurality of clock signals is coupled to a clock input of a respective one of said plurality of processors, said respective clock signal serving as a timing reference to coordinate the operations of said respective processor,
- wherein said clock IC comprises:
- a plurality of signal traces, each signal trace having a corresponding input end and a corresponding output end, each signal trace to propagate said respective clock signal received at the corresponding input end to the corresponding output end;
- a plurality of transmitters, with an output of each transmitter being coupled to a corresponding input end of a respective signal trace;
- and
- a plurality of receivers, with an input of each receiver being coupled to a corresponding output end of a respective signal trace,
- wherein each receiver comprises a self-biased inverter biased in a high-gain region,
- wherein a DC operating-point of each transmitter equals that of the corresponding receiver.
Dependencies are inferred from the claim text.