Hard error correction based on selective error counts in low-density parity check codes in memory devices

A system for improving a performance of an iterative decoder in a memory device, comprising:

• a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause the processor to:
• (a) determine a bin label sequence by reading, from at least one cell of the memory device, a noisy codeword using N soft-read channels that divide a voltage range associated with the at least one cell into M bins, wherein a bin label of the bin label sequence is an index of a bin of the M bins that corresponds to reading a respective bit of the noisy codeword using the N soft-read channels, and wherein N and M=N+1 are positive integers;
• (b) initialize a log-likelihood ratio (LLR) vector for each of the M bins, wherein each LLR of the LLR vector is represented using K bits, wherein a magnitude of an LLR for a first bin of the M bins and a last bin of the M bins is less than 2K-1−1, and wherein K is a positive integer;
• (c) generate an LLR sequence by applying the LLR vector to the bin label sequence;
• (d) perform a decoding iteration on the LLR sequence to generate a decoded data sequence;
• upon determining that a condition, indicative of the noisy codeword not being successfully decoded, is satisfied,
• (e) count hard errors in the decoded data sequence by incrementing at least one of multiple counters based on comparing corresponding elements of the decoded data sequence and the bin label sequence;
• and
• (f) update the LLR sequence by recalculating, based on the multiple counters, the LLR for the first bin and the LLR for the last bin;
• and
• (g) repeat operations (d) through (f) until the noisy codeword is successfully decoded or an index of the decoding iteration has exceeded a maximum number of decoding iterations,
• wherein the condition being satisfied comprises a checksum of the decoded data sequence being less than a first threshold.

A non-transitory computer-readable storage medium having instructions stored thereupon for improving a performance of a decoder in a memory device, comprising:

• (a) instructions for determining a bin label sequence by reading, from at least one cell of the memory device, a noisy codeword using N soft-read channels that divide a voltage range associated with the at least one cell into M bins, wherein a bin label of the bin label sequence is an index of a bin of the M bins that corresponds to reading a respective bit of the noisy codeword using the N soft-read channels, and wherein N and M=N+1 are positive integers;
• (b) instructions for initializing a log-likelihood ratio (LLR) vector for each of the M bins, wherein each LLR of the LLR vector is represented using K bits, wherein a magnitude of an LLR for a first bin of the M bins and a last bin of the M bins is less than 2K-1−1, and wherein K is a positive integer;
• (c) instructions for generating an LLR sequence by applying the LLR vector to the bin label sequence;
• (d) instructions for performing a decoding iteration on the LLR sequence to generate a decoded data sequence;
• in response to instructions for determining that a condition, indicative of the noisy codeword not being successfully decoded, is satisfied,
• (e) instructions for counting hard errors in the decoded data sequence by incrementing at least one of multiple counters based on comparing corresponding elements of the decoded data sequence and the bin label sequence;
• and
• (f) instructions for updating the LLR sequence by recalculating, based on the multiple counters, the LLR for the first bin and the LLR for the last bin;
• and
• (g) instructions for repeating operations (d) through (f) until the noisy codeword is successfully decoded or an index of the decoding iteration has exceeded a maximum number of decoding iterations,
• wherein the condition being satisfied comprises a checksum of the decoded data sequence being less than a first threshold.