Enhanced pci express (pcie) forward error correction (fec)
AssigneeMicrochip Technology Incorporated
InventorPeter Graumann
Life of this patent
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AssigneeMicrochip Technology Incorporated
InventorPeter Graumann
Estimating the term…
Disclosed herein are apparatus, system, method, and computer-readable medium aspects for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system. An example method may include receiving an FEC block comprising interleaved Reed-Solomon (RS) codewords, decoding the FEC block using a standard decoder to correct up to three successive RS symbol errors, and if the standard decoder fails, attempting error correction using one or more parallel decoders, comprising at least a 4-burst decoder to correct a single burst error spanning four RS symbols. The method may include selecting a corrected FEC block from an output of one of the standard decoder and the one or more parallel decoders based on successful error correction. The one or more parallel decoders can further comprise a 5-burst decoder and a 6-burst decoder.
An apparatus for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system, the apparatus comprising:
A method for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system, the method comprising:
An apparatus for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system, the apparatus comprising:
Dependencies are inferred from the claim text.