Hybrid successive approximation register analog-to-digital converter

A receiver, comprising:

• an analog front end (AFE) configured to condition an analog signal;
• a successive approximation analog-to-digital converter (SAR ADC) configured to generate a digital signal from the analog signal;
• and
• a digital signal processor configured to process the digital signal;
• wherein the SAR ADC comprises:
• a comparator having a first input, a second input, and an output, the comparator configured to compare the first input and the second input to generate the output;
• a first digital-to-analog converter (DAC) coupled to the first input of the comparator, the first DAC including a first plurality of unsplit capacitors and at least one first split capacitor;
• a second DAC coupled to the second input of the comparator, the second DAC including a second plurality of unsplit capacitors and at least one second split capacitor;
• and
• first switches coupled to the first DAC;
• second switches coupled to the second DAC;
• and
• a first circuit configured to, in response to the output of the comparator, generate control signals for the first and second switches.

An analog-to-digital converter (ADC), comprising:

• a comparator having an input and an output;
• a capacitive digital-to-analog converter (DAC) coupled to the input of the comparator;
• a first circuit coupled to the output of the comparator;
• wherein the capacitive DAC includes a plurality of unsplit capacitors, at least one split capacitor, and first switches coupled to the plurality of unsplit capacitors and the at least one split capacitor;
• and
• wherein the first circuit is configured to, in response to the output of the comparator, generate control signals for the switches.