Programmable high-speed frequency divider

A method for generating an output signal proportional to an input signal by a frequency division factor, the method comprising:

• receiving the input signal oscillating at a reference frequency;
• dividing the input signal by a clock reduction factor to generate a reduced frequency clock;
• generating an initial programmed count based on the frequency division factor and the clock reduction factor;
• generating a frequency divided signal based on the initial programmed count at an asynchronous clock divider receiving the reduced frequency clock;
• generating a plurality of phases of the reduced frequency clock;
• determining, at clock selection circuitry, a selected phase of the plurality of phases based on a selection signal;
• and
• generating the output signal based on the frequency divided signal generated by the asynchronous clock divider and the selected phase of the plurality of phases.

A phase-locked loop configured to generate a phase-locked signal based on a reference signal, comprising:

• a voltage-controlled oscillator configured to generate the phase-locked signal based on an oscillator voltage signal;
• a low-pass filter electrically connected to the voltage-controlled oscillator and configured to generate the oscillator voltage signal based on a charge pump output signal;
• a charge pump circuit electrically connected to the low-pass filter and configured to generate the charge pump output signal based on an up output signal and a down output signal from a phase frequency detector;
• a phase frequency detector circuit configured to generate the up output signal and the down output signal, based on a phase difference between the reference signal and a feedback signal;
• and
• a high-speed frequency divider, configured to generate the feedback signal proportional to the phase-locked signal by a frequency division factor, comprising:
• a reduced frequency clock oscillating at a reduced frequency, wherein the reduced frequency clock is generated by dividing the phase-locked signal by a clock reduction factor;
• an asynchronous clock divider configured to update an initial programmed count in synchronization with the reduced frequency clock and generate a frequency divided signal based on the initial programmed count,
• wherein the initial programmed count is based on the frequency division factor and the clock reduction factor;
• and
• clock selection circuitry configured to receive a plurality of phases of the reduced frequency clock and a selection signal indicating a selected phase of the plurality of phases;
• wherein the feedback signal is based on the frequency divided signal generated by the asynchronous clock divider and the selected phase of the plurality of phases.