Adaptive bandwidth tracking in phase locked loop which tracks reference and vco frequency
AssigneeNXP USA, Inc.
InventorsSaurabh Goyal, Anand Kumar Sinha, Ateet Omer
Life of this patent
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Abstract
A PLL method and apparatus are provided with a phase-frequency detector, charge pump, loop filter, voltage controlled ring oscillator, and feedback clock divider that is configured with a multiplication feedback integer (MFI) value for generating a PLL clock output signal, where the charge pump includes a current bias circuit which dynamically scales an input reference current under control of the MFI value to generate the charge pump control current so that a PLL bandwidth of the PLL adaptively tracks a frequency of the input reference signal and a frequency of the PLL clock output signal.
Claims20
A phase-locked loop (PLL), comprising:
- a phase-frequency detector (PFD) connected to receive an input reference signal and a feedback clock signal as inputs and configured to produce a PFD error output signal;
- a charge pump connected to receive the PFD error output signal as an input and configured to produce a charge pump control current which tracks a multiplication feedback integer (MFI) value;
- a loop filter connected to receive the charge pump control current and configured to produce a voltage control signal by filtering the charge pump control current;
- a voltage controlled ring oscillator which is connected to receive voltage control signal and configured to produce a PLL clock output signal;
- and
- a feedback clock divider connected to receive the PLL clock output signal as an input and configured with the MFI value to produce the feedback clock signal for return to the phase-frequency detector,
- where the charge pump comprises a current bias circuit which dynamically scales an input reference current under control of the MFI value to generate the charge pump control current so that a PLL bandwidth of the PLL adaptively tracks a frequency of the input reference signal and a frequency of the PLL clock output signal.
A method of operating a phase locked loop (PLL) circuit with adaptive bandwidth tracking, comprising:
- generating a phase-frequency error measure at a phase-frequency detector by detecting a phase difference between an input reference signal and a feedback clock signal;
- generating a charge pump control current which tracks a multiplication feedback integer (MFI) value in response to the phase-frequency error measure;
- filtering the charge pump control current with a loop filter to produce a voltage control signal;
- generating a PLL clock output signal with a voltage controlled oscillator in response to the voltage control signal;
- and
- providing the PLL clock output signal to a feedback clock divider which is configured with the MFI value to produce the feedback clock signal for return to the phase-frequency detector,
- where the charge pump dynamically scales an input reference current under control of the MFI value to generate the charge pump control current so that a PLL bandwidth of the PLL circuit adaptively tracks a frequency of the input reference signal and a frequency of the PLL clock output signal.
A phase locked loop (PLL) comprising a phase-frequency detector connected to receive an input reference signal and a feedback clock signal as inputs, a charge pump connected to receive a phase-frequency detector error output signal from the phase-frequency detector, a second order loop filter connected to receive a charge pump control current from the charge pump, a voltage controlled oscillator connected to receive a voltage control signal from the second order loop filter and configured to generate a PLL clock output signal, and a feedback clock divider connected to receive the PLL clock output signal and configured with a multiplication feedback integer (MFI) value to generate the feedback clock signal, where the charge pump is configured to generate the charge pump control current which dynamically tracks the MFI value with a current bias circuit which scales an input reference current under control of the MFI value to generate the charge pump control current so that a PLL bandwidth of the PLL adaptively tracks a frequency of the input reference signal to the PLL and a frequency of the PLL clock output signal.
Dependencies are inferred from the claim text.