Bus training using multiple flip-flops and clock signals

A method, comprising:

• receiving, at bus training circuitry, data from a bus;
• latching the data at a first plurality of flip-flops of the bus training circuitry utilizing a first clock signal;
• providing the data from the first plurality of flip-flops to XOR circuitry of the bus training circuitry, wherein the XOR circuitry is coupled to the first plurality of flip-flops;
• providing the data from the XOR circuitry to a second plurality of flip-flops of the bus training circuitry, wherein the XOR circuitry is coupled to the second plurality of flip-flops;
• latching the data at the second plurality of flip-flops utilizing a second clock signal;
• and
• providing the data from the second plurality of flip-flops for training of a timing of the bus.

An apparatus, comprising:

• bus training circuitry coupled to a bus and comprising:
• a plurality of first delay elements;
• a second delay element;
• and
• a third delay element, wherein the plurality of first delay elements are coupled to the second delay element and the third delay element is coupled to the second delay element;
• wherein the bus training circuitry is configured to:
• receive a first clock signal and a second clock signal, wherein the first clock signal is an even clock signal and the second clock signal is an odd clock signal;
• provide the first clock signal and the second clock signal to the plurality of first delay elements;
• provide the first clock signal and the second clock signal to a plurality of gates from the plurality of first delay elements;
• combine the first clock signal and the second clock signal utilizing the plurality of gates;
• provide a combined clock signal from the plurality of gates to the second delay element;
• provide a first clock signal from the second delay element to a first plurality of flip-flops and to a third delay element;
• provide a second clock signal from the third delay element to a second plurality of flip-flops;
• and
• wherein the first clock signal and the second clock signal are utilized by the first plurality of flip-flops and the second plurality of flip-flops to latch data used to train a timing of a bus.