US 2026/0213751 A1 · TERNARY LOGIC GATE CIRCUIT, COMPUTING CIRCUIT, CHIP, AND ELECTRONIC DEVICE

Abstract

This disclosure provides a ternary logic gate circuit, a computing circuit, a chip, and an electronic device. The ternary logic gate circuit provided in this disclosure can add 1 to and subtract 1 from an input logical value. On the basis of the ternary logic gate circuit, the ternary logic gate circuit is applied to a ternary logic circuit by using 27 single-variable functions of three-valued logic, so that a structure of the ternary logic circuit can be simplified, a quantity of transistors in the ternary logic circuit can be reduced, power consumption of the ternary logic circuit can be reduced, and computing efficiency of the ternary logic circuit can be improved.

Claims20

Dependent claims

A ternary logic gate circuit, comprising:

a first voltage module configured to output a first voltage, wherein the first voltage indicates a first logical value, and the first logical value is any logical value in ternary logical values;
and
a logic gate module configured to:
receive the first voltage, and output a second voltage, wherein the second voltage indicates a second logical value, and the second logical value is equal to the first logical value plus 1 or minus 1.

1 more element

An adder circuit, comprising:

a first ternary logic gate circuit;
and
a second ternary logic gate circuit, wherein the first ternary logic gate circuit or the second ternary logic gate circuit comprises a first voltage module and a logic gate module, wherein a first voltage module configured to output a first voltage, wherein the first voltage indicates a first logical value, and the first logical value is any logical value in ternary logical values;
and
a logic gate module configured to:
receive the first voltage and output a second voltage, wherein the second voltage indicates a second logical value equal to the first logical value plus 1 or minus 1, wherein in the first ternary logic gate circuit, the second logical value is equal to the first logical value plus 1, and in the second ternary logic gate circuit, the second logical value is equal to the first logical value minus 1.

3 more elements

A half-adder circuit, comprising:

a adder circuit comprising a first ternary logic gate circuit and a second ternary logic gate circuit, wherein the first ternary logic gate circuit or the second ternary logic gate circuit comprises:
a first voltage module configured to output a first voltage, wherein the first voltage indicates a first logical value, and the first logical value is any logical value in ternary logical values;
and
a logic gate module configured to receive the first voltage and output a second voltage, wherein the second voltage indicates a second logical value, and the second logical value is equal to the first logical value plus 1 or minus 1, wherein in the first ternary logic gate circuit, the second logical value is equal to the first logical value plus 1, and in the second ternary logic gate circuit, the second logical value is equal to the first logical value minus 1.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

19/567,733Filed 16 Mar 2026

Priority

CN 202311209872.418 Sep 2023

Published

23 Jul 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H03K 19/0002
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: multistate logic
G06F 7/49
Using non-contact-making devices, e.g. tube, solid state device; using unspecified devices: computations with a radix, other than binary, 8, 16 or…
G06F 7/501
Adding; Subtracting: half or full adders, i.e. basic adder cells for one denomination
H03K 19/08
Using specified components: using semiconductor devices

Ternary logic gate circuit, computing circuit, chip, and electronic device

Life of this patent

Ternary logic gate circuit, computing circuit, chip, and electronic device

Life of this patent

Abstract

Claims20