Driver chip, semiconductor package and method for driving a pow-er transistor
AssigneeInfineon Technologies Austria AG
InventorsMichael SIEBERER, Thomas FERIANZ
Life of this patent
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Abstract
A driver chip configured to drive a gate of a power transistor comprises: a slope reference configured to provide a first voltage, an output configured to be connected to a gate terminal of a power transistor, a shaping capacitor configured to be connected between the slope reference and a drain terminal of the power transistor, and a buffer connected between the slope reference and the output and configured to be provided with the first voltage.
Claims19
A driver chip configured to drive a gate of a power transistor, the driver chip comprising:
- a slope reference generator configured to provide a first voltage,
- an output node configured to drive a gate terminal of a power transistor,
- a shaping capacitor connected between the slope reference generator and a drain terminal of the power transistor, and
- a buffer connected between the slope reference generator and the output node, the buffer configured to receive the first voltage.
A driver chip configured to drive a gate of a power transistor, the driver chip comprising:
- a slope reference generator configured to provide a first voltage,
- an output node operative to drive a gate terminal of a power transistor, and
- a shaping capacitor connected between the slope reference generator and a drain terminal of the power transistor device,
- wherein the shaping capacitor includes a diode.
A method for driving a power transistor, the method comprising:
- providing a driver chip and a power chip, the power chip comprising a power transistor,
- providing, using a slope reference generator of the driver chip, a first voltage,
- connecting an output node of the driver chip to a gate terminal of the power transistor,
- connecting a shaping capacitor of the driver chip between the slope reference generator and a drain terminal of the power transistor,
- driving a gate of the power transistor using the first voltage, wherein the shaping capacitor shapes a transition between an on state and an off state of the power transistor, and
- using a buffer of the driver chip to buffer the shaping capacitor from a gate-drain capacitance of the power transistor, wherein the first voltage is provided from the applet node of the driver chip to an input of the buffer.
Dependencies are inferred from the claim text.