Circuits and methods for leakage reduction in mos devices

A low voltage regulator, comprising:

• a PMOS transistor device comprising a source terminal coupled to a supply voltage, a drain terminal configured to be coupled to a load, and a gate terminal;
• an error amplifier comprising an output coupled to the gate terminal, the error amplifier powered by the supply voltage;
• and
• a voltage switching circuit configured to selectively couple a first high voltage that is higher than the supply voltage to the output of the error amplifier;
• wherein
• in a first mode, the voltage switching decouples the first high voltage from the output of the error amplifier, and
• in a second mode, the voltage switching circuit couples the first high voltage to the output of the error amplifier.

A method of controlling a low voltage regulator comprising a PMOS pass device coupled between a supply voltage and an output terminal, the method comprising:

• regulating a current through the PMOS pass device by adjusting a control voltage at a gate terminal;
• during a first mode of operation, decoupling a high voltage from the gate terminal to limit the control voltage at the gate terminal to a maximum value defined by the supply voltage;
• and
• during a second mode of operation, coupling the high voltage to the gate terminal, wherein the high voltage is greater than the supply voltage, to drive the control voltage at the gate terminal to a value higher than the supply voltage.