Memory system for detecting fault in signal transmission path
AssigneeSK hynix Inc.
InventorsChang Kwon LEE, Haeng Seon CHAE, Hong Seok CHOI
Life of this patent
Estimating the term…
Abstract
A memory system includes a base die configured to control operations of a plurality of core dies. The base die applies a command address to a command address through silicon via (TSV) by receiving the command address through a first signal transmission path after the start of a wafer test operation, outputs a latch command address generated based on a logic level of the command address TSV as data through a second signal transmission path after the start of a read operation, and detects a fault in the first signal transmission path based on a logic level of the data.
Claims26
A memory system comprising:
- a base die configured to control operations of a plurality of core dies;
- a processor connected to the base die through an interposer,
- wherein the base die is further configured to:
- apply a command address to a command address through silicon via (TSV) by receiving the command address through a first signal transmission path after a start of a wafer test operation;
- output a latch command address generated based on a logic level of the command address TSV as data through a second signal transmission path after a start of a read operation;
- and
- detect a fault in the first signal transmission path based on a logic level of the data.
A memory system comprising:
- a base die configured to control operations of a plurality of core dies;
- a processor connected to the base die through an interposer,
- wherein the base die is further configured to:
- apply a command address to a command address through silicon via (TSV) by receiving the command address through a first signal transmission path after a start of a wafer test operation;
- output a latch command address generated based on a logic level of the command address TSV as data through a second signal transmission path;
- apply the data to a data TSV by receiving the data through the second signal transmission path;
- output transfer data generated based on a logic level of the data TSV as the data through the second signal transmission path;
- and
- detect a fault in the first signal transmission path and the second signal transmission path based on a logic level of the data.
A memory system comprising:
- a base die configured to control operations of a plurality of core dies;
- a processor connected to the base die through an interposer,
- wherein the base die is further configured to:
- sequentially apply a command address to a plurality of command address through silicon vias (TSVs) by receiving the command address through a plurality of first signal transmission paths after a start of a wafer test operation;
- sequentially output a plurality of latch command addresses generated based on logic levels of the plurality of command address TSVs as data through a second signal transmission path after a start of a read operation;
- and
- detect a fault in the plurality of first signal transmission paths based on a logic level of the data.
A base die comprising:
- a data (DA) pad region configured to receive a command address and configured to input and output data;
- a physical region configured to generate an internal command address by receiving the command address;
- a through silicon via (TSV) region configured to apply the internal command address to a command address TSV and configured to generate a latch command address based on a logic level of the command address TSV;
- and
- a data input and output circuit configured to generate the data based on the latch command address after a start of a read operation of a wafer test operation and configured to output the data to the DA pad region,
- wherein the base die detects a fault in the physical region and the TSV region based on a logic level of the data.
Dependencies are inferred from the claim text.