Memory device including digital phase-locked loop mounted in physical interface, and semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsYongsun Lee, Daihyun Lim, Insung Kim, Sungho Lee
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Abstract
A memory device has a physical interface (PHY) including a digital phase-locked loop (DPLL), and a semiconductor package. The memory device includes a base die and at least one core die. The base die includes a direct access (DA) region configured to receive a test clock signal from an outer environment via a pad and a PHY including at least one DPLL configured to generate an output clock signal by changing capacitance of a capacitor bank of a digitally-controlled oscillator (DCO) based on a pulse width modulation (PWM) signal according to a phase difference between the test clock signal and a feedback signal.
Claims20
A memory device comprising:
- a base die and at least one core die,
- wherein the base die comprises:
- a direct access (DA) region configured to receive a test clock signal via a pad;
- and
- a physical interface (PHY) comprising at least one digital phase-locked loop (DPLL), and
- wherein the at least one DPLL is configured to generate an output clock signal by changing capacitance of a capacitor bank of a digitally-controlled oscillator (DCO) based on a pulse width modulation (PWM) signal according to a phase difference between the test clock signal and a feedback signal.
A memory device comprising a base die and at least one core die,
- wherein the base die comprises:
- a direct access (DA) region configured to receive a test clock signal via a pad;
- and
- a physical interface (PHY) comprising at least one digital phase-locked loop (DPLL) configured to generate an output clock signal based on the test clock signal, and
- wherein the at least one DPLL comprises:
- a time-to-digital converter (TDC) configured to convert a phase difference between the test clock signal and a feedback signal into a digital signal;
- a digital loop filter (DLF) configured to, based on the digital signal, generate a digital code to adjust a duty ratio for a first period corresponding to a cycle of the feedback signal;
- a pulse width modulation (PWM) configured to, based on the digital code, generate a PWM signal having the duty ratio;
- a digitally-controlled oscillator (DCO) configured to adjust an output frequency of the output clock signal by changing capacitance of a capacitor bank based on the PWM signal;
- and
- a divider configured to generate the feedback signal by dividing the output clock signal.
A semiconductor package comprising:
- a substrate;
- at least one memory device on the substrate and comprising a base die and at least one core die;
- and
- a processing chip on the substrate and configured to output a clock signal to the base die,
- wherein the base die comprises:
- a physical interface (PHY) comprising at least one digital phase-locked loop (DPLL) configured to generate an output clock signal by changing capacitance of a capacitor bank of a digitally-controlled oscillator (DCO) based on a pulse width modulation (PWM) signal according to a phase difference between the clock signal and a feedback signal;
- and
- a through silicon via (TSV) region configured to communicate with the at least one core die.
Dependencies are inferred from the claim text.