Memory built-in self-test having an adaptable access protocol
AssigneeGoogle Inc.
InventorsMayank Parasrampuria, Samuel Tien-en Lee
Life of this patent
Estimating the term…
Abstract
A system on a chip can include a memory, a clock generating a clock signal, and an MBIST controller that issues read/write commands, according to the clock signal, to test the memory. The disclosed system on a chip further includes a clock-decoupling circuit positioned between the clock and the MBIST controller. The clock-decoupling circuit can be configured to decouple the clock from the MBIST controller after a read/write command is issued and until an operation complete signal is received from a multi-cycle access control module. The clock-decoupling circuit allows the MBIST controller to adapt to the multi-cycle access protocol run by the multi-cycle access control module without having to be programmed with its details.
Claims20
A system on a chip comprising:
- a memory;
- a clock configured to generate a clock signal;
- an MBIST controller configured to generate a read/write command to test the memory;
- a multi-cycle access control module coupled between the MBIST controller and the memory, the multi-cycle access control module configured to:
- receive the read/write command from the MBIST controller;
- transmit a clock pulse to the memory in response to the read/write command;
- and
- generate an operation-complete signal a number of clock cycles after the clock pulse;
- and
- a clock-decoupling circuit coupled between the clock and the MBIST controller, the clock-decoupling circuit configured to:
- decouple the clock from the MBIST controller based on the read/write command;
- and
- recouple the clock to the MBIST controller based on the operation-complete signal.
A method for performing a test of a memory, comprising:
- activating an MBIST controller programmed to execute a sequence of operations, the sequence of operations timed according to pulses of a clock signal received at the MBIST controller;
- transmitting a read/write command from the MBIST controller to the memory;
- decoupling the clock signal from the MBIST controller based on the read/write command to pause the sequence of operations;
- determining that a read/write operation, triggered by the read/write command, is complete;
- and
- recoupling the clock signal to the MBIST controller based on the read/write operation being complete to restart the sequence of operations.
A MBIST core for a system on a chip, the MBIST core comprising:
- an MBIST controller including a finite state machine configured to execute a sequence of operations according to clock pulses of a clock received at the MBIST controller;
- and
- a clock-decoupling circuit coupled to a clock terminal of the MBIST controller, the clock-decoupling circuit configured to:
- decouple the clock pulses of the clock from the clock terminal of the MBIST controller after a read/write command is transmitted to a memory;
- and
- recouple the clock pulses of the clock to the clock terminal of the MBIST controller after a read/write operation of the memory, which was triggered by the read/write command, is complete.
Dependencies are inferred from the claim text.