Memory device and method of operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJi-Kuan Lee, Chia-En Huang, Yao-Jen Yang, Ting-Wei Chiang
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Abstract
Provided is a memory device including: a first memory cell disposed over an active region. The first memory cell may include: a first transistor comprising: a first gate structure extending across the active region, a first source/drain structure and a second source/drain structure disposed on the active region at opposite sides of the first gate structure; and a first anti-fuse structure connected in series with the first transistor, and comprising: a first electrode over the first source/drain structure, the first source/drain structure used as a second electrode and a first insulator vertically sandwiched between the first electrode and the second electrode.
Claims20
A memory device, comprising:
- a first memory cell, disposed over an active region and comprising:
- a first transistor comprising:
- a first gate structure extending across the active region, a first source/drain structure and a second source/drain structure disposed on the active region at opposite sides of the first gate structure;
- and
- a first anti-fuse structure connected in series with the first transistor, and comprising:
- a first electrode over the first source/drain structure, the first source/drain structure used as a second electrode and a first insulator vertically sandwiched between the first electrode and the second electrode.
A memory device, comprising:
- an active region extending along a first direction;
- a first gate structure extending along a second direction different from the first direction and across the active region to divide the active region into a first source/drain structure and a second source/drain structure;
- an insulator overlying the first source/drain structure;
- a first interconnect structure overlying the second source/drain structure;
- and
- a first via vertically disposed on the insulator and separated from the first source/drain structure by the insulator to form a first anti-fuse structure.
A method for operating a memory device, comprising:
- providing a first memory cell over an active region and the first memory cell comprising:
- a first transistor comprising:
- a first gate structure extending across the active region, a first source/drain structure and a second source/drain structure disposed on the active region at opposite sides of the first gate structure;
- and
- a first anti-fuse structure connected in series with the first transistor, and comprising:
- a first electrode over the first source/drain structure, the first source/drain structure used as a second electrode and a first insulator vertically sandwiched between the first electrode and the second electrode;
- activating the first transistor of the first memory cell by applying a first voltage to the first gate structure of the first transistor;
- and
- breaking down the first insulator by applying a second voltage on the first electrode, thereby programming the first memory cell.
Dependencies are inferred from the claim text.