Charge trapping nor flash memory for stacked memory architectures

A memory system, comprising:

• a stack of memory dies comprising a logic die coupled with a plurality of NOR memory dies and a plurality of volatile memory dies;
• and
• processing circuitry coupled with the stack of memory dies and configured to cause the memory system to:
• receive, at the logic die, a plurality of access commands directed to one or more model parameters associated with an artificial intelligence (AI) model, wherein the AI model is operated by the processing circuitry;
• obtain, at the logic die, the one or more model parameters from the plurality of NOR memory dies in accordance with receiving the plurality of access commands;
• and
• transmit, from the logic die, the one or more model parameters to the processing circuitry in response to obtaining the one or more model parameters from the plurality of NOR memory dies.

A method for operating a memory system, comprising:

• receiving, at a logic die of a stack of memory dies, a plurality of access commands directed to one or more model parameters associated with an artificial intelligence (AI) model, wherein the AI model is operated by processing circuitry coupled with the stack of memory dies, and wherein the stack of memory dies comprises a plurality of NOR memory dies and a plurality of volatile memory dies;
• obtaining, at the logic die, the one or more model parameters from the plurality of NOR memory dies in accordance with receiving the plurality of access commands;
• and
• transmitting, from the logic die, the one or more model parameters to the processing circuitry in response to obtaining the one or more model parameters from the plurality of NOR memory dies.