Semiconductor memory device

A semiconductor memory device comprising:

• a control circuit;
• a first word line;
• and
• a memory array including a first memory cell connected to the first word line and configured to store n bits (where n is an integer equal to or greater than one),
• wherein the control circuit is configured to
• execute a first write operation in response to a first write instruction from an external memory controller, execute a second write operation in response to a second write instruction from the external memory controller, execute a first read operation in response to a first read instruction from the external memory controller, and execute a second read operation in response to a second read instruction from the external memory controller,
• control, by executing the first write operation, a threshold voltage of the first memory cell to fall within any of 2n distributions including a first distribution and a second distribution arranged in an order of increasing voltage,
• determine, by executing the first read operation, whether the threshold voltage of the first memory cell falls within the first distribution or the second distribution, on the basis of a first voltage,
• control, by executing the second write operation, the threshold voltage of the first memory cell to fall within any of 2n distributions including a third distribution and a fourth distribution arranged in an order of increasing voltage, and
• determine, by executing the second read operation, whether the threshold voltage of the first memory cell falls within the third distribution or the fourth distribution, on the basis of a second voltage higher than the first voltage, and
• at least a part of the third distribution exists between the first distribution and the second distribution.