Flash and method for controlling program voltage of same

A method for controlling a program voltage of a flash, wherein the flash comprises a plurality of memory cells, the plurality of memory cells are arranged to form an array structure of the flash, and all the memory cells in the array structure are arranged in rows and columns;

• all the memory cells of the same column are connected in parallel between two adjacent bit lines;
• for a selected memory cell, two bit lines connected to the selected memory cell are a first bit line and a second bit line respectively, and the first bit line is a bit line on a side close to a selected memory bit of the selected memory cell;
• during a program operation on the selected memory bit of the selected memory cell, a bit line program voltage is applied to the first bit line;
• during the program operation, the method for controlling a program voltage comprises the following steps:
• configuring a first program stage to perform first-time program of the selected memory bit during the first program stage, wherein the bit line program voltage in the first program stage is set to a first positive voltage;
• configuring a second verify stage to verify a state of the selected memory bit during the second verify stage, wherein the bit line program voltage is set to 0 V;
• and
• configuring a third program stage to perform second-time program of the selected memory bit during the third program stage, wherein the bit line program voltage in the second program stage is set to a second positive voltage;
• in the second verify stage, if a verification result is normal, the third program stage is omitted;
• if the verification result is abnormal, the third program stage is performed;
• the bit line program voltages required by all the memory cells in the array structure to achieve normal program are different;
• the first positive voltage is less than the second positive voltage, the first positive voltage satisfies a requirement of programing a first part of the memory cells in the array structure, and program disturb is reduced by reducing the first positive voltage;
• the first positive voltage cannot achieve normal program of a second part of the memory cells, the second positive voltage satisfies a requirement of programing the second part of the memory cells, a number of memory cells of the second part is less than a number of memory cells of the first part, and a cumulative effect of program disturb of the second positive voltage is alleviated by decreasing the number of memory cells of the second part.