Ultra-large scale in-memory computing core circuit for resolving ir-drop issues

A line resistance network circuit of a non-volatile memory array, comprising:

• a DAC module, comprising M DACs and voltage drivers connected to the M DACs, forming M DAC channels;
• a two-dimensional 1T1R array, having a word line control terminal WL parallel to a column current output terminal SL, wherein a bit line voltage signal input terminal BL is perpendicular to the word line control terminal WL and the column current output terminal SL, two adjacent columns of 1T1R constitute a differential pair of columns, which are provided for storing neural network weights;
• and
• an ADC module, comprising N ADC channels, each of the ADC channels comprising a dual-ended differential readout circuit and an ADC connected in sequence;
• wherein the DAC module is connected to the bit line voltage signal input terminal BL of the two-dimensional 1T1R array, and the column current output terminal SL of the two-dimensional 1T1R array is connected to the ADC module, a size of the two-dimensional 1T1R array is m×n, one of the ADC channels is shared by i rows in the array and controlled through time-division via a switch array, one of the DACs is shared by j columns in the array and controlled through time-division via the switch array, and j>i;
• the two-dimensional 1T1R array is configured in a rectangular layout, and a length of the rectangle is greater than a width of the rectangle;
• the dual-ended differential readout circuit adopts a folded cascode configuration as a differential input stage, with NMOS transistors serving as a common-source amplification output stage, which is utilized for voltage clamping and current isolation sampling of the two adjacent columns of 1T1R, the sampled current is converted into a voltage through a trimming resistance adjustment circuit.