Memory device
AssigneeSTMicroelectronics International N.V.
InventorsChristophe GONCALVES, Marc BATTISTA, Francois TAILLIET
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Abstract
The present disclosure relates to a memory device including a sense amplifier, wherein the amplifier comprises a first inverter, wherein an input and an output of the inverter are coupled to a first transistor configured to be switched on during a step of pre-charging of a memory cell.
Claims16
A memory device comprising:
- a sense amplifier comprising a first inverter and a NAND logic gate;
- wherein the first inverter comprises an input and an output and the sense amplifier is configured to have equal potentials on the input and the output of the first inverter during a pre-charging step of a memory cell;
- wherein the NAND logic gate has a first input coupled to the output of the first inverter, a second input coupled to an application node of a first voltage, and an output of the NAND logic gate coupled to an output of the sense amplifier;
- and
- wherein the first voltage is configured to be equal to a second reference voltage during the pre-charging step and to be equal to a third supply voltage during a step of reading the memory cell.
A method of controlling a memory device comprising a sense amplifier, wherein the sense amplifier comprises a first inverter and a NAND logic gate, wherein the first inverter comprises an input and an output and the sense amplifier is configured to have equal potential on the input and the output of the first inverter, the method comprising:
- equalizing, during a pre-charging step of a memory cell, a potential of the input and a potential of the output of the first inverter;
- wherein the NAND logic gate has a first input coupled to the output of the first inverter, a second input coupled to an application node of a first voltage, and an output of the NAND logic gate coupled to an output of the sense amplifier;
- and
- wherein the first voltage is configured to be equal to a second reference voltage during the pre-charging step and to be equal to a third supply voltage during a step of reading the memory cell.
Dependencies are inferred from the claim text.