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AssigneeSamsung Electronics Co., Ltd.
InventorsKangsub Jeong, Kyu-Chang Kang, Young Seok Park, Duckyoung Seo, Younghun Seo, Hoseok Lee
Estimating the term…
A memory device including: memory cells; bitlines connected to a portion of the memory cells; sense amplifiers respectively connected to the bitlines; and complementary bitlines connected to a second portion of the memory cells and respectively connected to the sense amplifiers. The sense amplifiers include first and second sense amplifiers. The bitlines include first and second bitlines adjacent to each other and respectively connected to the first and second sense amplifiers. The complementary bitlines include a first and second complementary bitlines connected to the first and second sense amplifiers. The first sense amplifier includes a first internal bitline. The first internal bitline connects to the first bitline during a sensing interval of a read operation. The second sense amplifier includes a second internal bitline adjacent to the first internal bitline. And, the second internal bitline connects to the second complementary bitline during the sensing interval.
A memory device comprising:
A memory device comprising:
A bitline sense amplifier circuit included in a memory device, the bitline sense amplifier circuit comprising:
Dependencies are inferred from the claim text.