Memory device and memory system including the same

A memory device comprising:

• a receiver circuit configured to process a data signal received from a memory controller and generate output data;
• and
• a control logic circuit configured to control the receiver circuit,
• wherein the receiver circuit comprises
• a buffer configured to compare the data signal to a reference voltage and generate an amplified signal,
• a summation circuit configured to generate a summation output signal based on the amplified signal, and
• a sampler comprising (i) a sampling circuit configured to generate a sampling signal by sampling the summation output signal based on a clock signal and (ii) an equalization circuit coupled to the sampling circuit and configured to equalize the sampling signal based on a feedback sampling signal sampled prior to the sampling signal, and
• wherein the equalization circuit comprises (i) a first transistor circuit configured to receive the feedback sampling signal and (ii) a second transistor circuit between the first transistor circuit and the sampling circuit, wherein the second transistor circuit is configured to receive a bias voltage associated with an equalization coefficient.

A memory system comprising:

• a memory device;
• and
• a memory controller configured to write data into the memory device or read out data stored in the memory device,
• wherein the memory device comprises
• a receiver circuit configured to process a data signal received from the memory controller and generate output data, and
• a control logic circuit configured to control the receiver circuit,
• wherein the receiver circuit comprises
• a buffer configured to compare the data signal to a reference voltage and generate an amplified signal,
• a summation circuit configured to generate a summation output signal based on the amplified signal, and
• a sampler comprising (i) a sampling circuit configured to generate a sampling signal by sampling the summation output signal based on a clock signal and (ii) an equalization circuit coupled to the sampling circuit and configured to equalize the sampling signal based on a feedback sampling signal sampled prior to the sampling signal, and
• wherein the equalization circuit comprises (i) a first transistor circuit configured to receive the feedback sampling signal and (ii) a second transistor circuit between the first transistor circuit and the sampling circuit, wherein the second transistor circuit is configured to receive a bias voltage associated with an equalization coefficient.