Memory device and memory system including the same

A memory device, comprising:

• a receive circuit configured to process a data signal from a memory controller and generate output data;
• and
• a control logic circuit configured to control the receive circuit and generate an offset compensation signal for the receive circuit,
• wherein the receive circuit comprises:
• a buffer configured to compare the data signal to a reference voltage and generate an amplified signal;
• a summer configured to generate a summer output signal based on the amplified signal;
• and
• a sampler comprising (i) a sampling circuit configured to sample the summer output signal based on a clock signal and generate a sampling signal, and (ii) a first equalization circuit structure connected to the sampling circuit and configured to equalize the sampling signal based on a feedback sampling signal, wherein the sampling circuit is configured to generate the feedback sampling signal prior to the sampling signal, and
• wherein the first equalization circuit structure comprises:
• a first transistor configured to receive the feedback sampling signal;
• a second transistor structure between the first transistor and the sampling circuit and configured to receive a bias voltage associated with an equalization coefficient;
• and
• a third transistor structure between the first transistor and the sampling circuit and configured to receive the offset compensation signal for the sampler.

A memory system, comprising:

• a memory device;
• and
• a memory controller configured to write data to the memory device or read data stored in the memory device,
• wherein the memory device comprises:
• a receive circuit configured to process a data signal from the memory controller and generate output data;
• and
• a control logic circuit configured to control the receive circuit and generate an offset compensation signal for the receive circuit,
• wherein the receive circuit comprises:
• a buffer configured to compare the data signal to a reference voltage and generate an amplified signal;
• a summer configured to generate a summer output signal based on the amplified signal;
• and
• a sampler comprising (i) a sampling circuit configured to sample the summer output signal based on a clock signal and generate a sampling signal, and (ii) a first equalization circuit structure connected to the sampling circuit and configured to equalize the sampling signal based on a feedback sampling signal, wherein the sampling circuit is configured to generate the feedback sampling signal prior to the sampling signal, and
• wherein the first equalization circuit structure comprises:
• a first transistor configured to receive the feedback sampling signal;
• a second transistor structure between the first transistor and the sampling circuit and configured to receive a bias voltage associated with an equalization coefficient;
• and
• a third transistor structure between the first transistor and the sampling circuit and configured to receive the offset compensation signal for the sampler.