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US 2026/0212909 A1Published application
Memory device and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorYoungjae KIM
Life of this patent
Estimating the term…
Abstract
A memory device includes a power gating circuit for connecting a peripheral circuit to or disconnecting the peripheral circuit from a power supply voltage line in response to a power gating enable signal. The power gating circuit may include a boosting control circuit configured to, when a command indicates a standby mode, boost a gate voltage of a positive power gating switch to a first voltage level during a first stage and then boost the gate voltage of the positive power gating switch to a second voltage level during a second stage.
Claims20
A memory device comprising:
- a memory cell array comprising memory cells;
- a peripheral circuit configured to transmit a plurality of signals for writing or reading data to the memory cells;
- a control logic circuit configured to output a power gating enable signal;
- and
- a power gating circuit configured to, in response to the power gating enable signal, connect the peripheral circuit to or disconnect the peripheral circuit from a power supply voltage line,
- wherein the power gating circuit comprises:
- a positive power gating switch connected between the peripheral circuit and the power supply voltage line;
- and
- a boosting control circuit configured to boost a gate voltage of the positive power gating switch to a first voltage level during a first stage and then boost the gate voltage of the positive power gating switch to a second voltage level higher than the first voltage level during a second stage after the first stage, in a standby mode.
6 more elements
A memory device comprising:
- a memory cell array comprising memory cells;
- a peripheral circuit configured to transmit a plurality of signals for writing or reading data to the memory cells;
- a control logic circuit configured to output a power gating enable signal;
- and
- a power gating circuit configured to, in response to the power gating enable signal, connect the peripheral circuit to or disconnect the peripheral circuit from a ground voltage line,
- wherein the power gating circuit comprises:
- a negative power gating switch connected between the peripheral circuit and the ground voltage line;
- and
- a dropping control circuit configured to drop a gate voltage of the negative power gating switch to a first voltage level during a first stage and then drop the gate voltage of the negative power gating switch to a second voltage level lower than the first voltage level during a second stage after the first stage, in a standby mode.
6 more elements
A memory system comprising:
- a host device configured to transmit a command indicating a standby mode;
- and
- a memory device configured to operate in the standby mode in response to the command,
- wherein the memory device comprises:
- a memory cell array comprising memory cells;
- a peripheral circuit configured to transmit a plurality of signals for writing or reading data to the memory cells;
- a control logic circuit configured to output a power gating enable signal in response to the command;
- and
- a power gating circuit configured to, in response to the power gating enable signal, connect the peripheral circuit to or disconnect the peripheral circuit from a power supply voltage line,
- wherein the power gating circuit comprises:
- a positive power gating switch connected between the peripheral circuit and the power supply voltage line;
- and
- a boosting control circuit configured to boost a gate voltage of the positive power gating switch to a first voltage level during a first stage and then boost the gate voltage of the positive power gating switch to a second voltage level higher than the first voltage level during a second stage after the first stage.
10 more elements
Dependencies are inferred from the claim text.