Semiconductor memory devices, memory systems and memory dies

A memory system comprising:

• a semiconductor memory device including a plurality of memory dies;
• and
• a memory controller configured to control the semiconductor memory device, and
• wherein the semiconductor memory device includes:
• an external resistor in a board;
• and
• the plurality of memory dies on the board, the plurality of memory dies including a master die and a plurality of slave dies,
• wherein the master die includes a first output driver and a first communication pad, and the master die is configured to during an impedance calibration interval:
• determine, based on a first power supply voltage, a first control code set associated with the first output driver;
• latch the first control code set;
• generate a first done signal indicating that the first control code set is determined;
• transmit the first done signal to a first slave die of the plurality of slave dies through the first communication pad;
• based on the first done signal, determine a second control code set associated with the first output driver based on a second power supply voltage;
• and
• latch the second control code set.

A memory die comprising:

• an output driver;
• an impedance calibration circuit connected to an external resistor through an impedance pad, the impedance calibration circuit being configured to during an impedance calibration interval:
• determine, based on a first power supply voltage, a first control code set associated with a driving strength of the output driver;
• latch the first control code set;
• generate a first done signal indicating that the first control code set is determined;
• transmit the first done signal through a communication pad;
• based on the first done signal, determine, based on a second power supply voltage, a second control code set associated with the driving strength of the output driver;
• and
• latch the second control code set;
• a power selection circuit configured to receive the first power supply voltage and the second power supply voltage, provide the first power supply voltage to the impedance calibration circuit, and provide, based on the first done signal, the second power supply voltage to the impedance calibration circuit;
• a data input/output (I/O) circuit including the output driver;
• a first power switch configured to provide the first power supply voltage to the data I/O circuit based on a power selection signal;
• and
• a second power switch configured to provide the second power supply voltage to the data I/O circuit based on an inverted version of the power selection signal.