Channel-less distributed design-for-test architecture

A method performed by an integrated circuit device, comprising:

• communicating design-for-test (DFT) data between a plurality of hardware modules (HMs) via a bus, wherein the plurality of HMs includes a center HM;
• executing DFT operations at each of the plurality of HMs using DFT circuitry comprising a scan shift network (SSN) and an encoder/decoder for test (EDT) circuit;
• and
• managing SSN connections for the plurality of HMs using SSN multiplexing circuitry in the center HM.

An apparatus implementing a distributed test architecture, the apparatus comprising:

• a channel wrapper tile having a plurality of communication channels, the channel wrapper tile comprising:
• an encoder/decoder for test (EDT) circuit positioned in a center region of the channel wrapper tile;
• a scan shift network (SSN) circuit positioned in the center region of the channel wrapper tile;
• on-chip clock (OCC) circuitry positioned at one or more input interfaces of the plurality of communication channels;
• and
• a test communication bus coupled to the EDT circuit and the SSN circuit, the test communication bus configured to communicate design-for-test (DFT) data with other hardware modules.