# US 2026/0211831 A1 · PROVIDING FLEXIBLE LINK WIDTH (FLW) DUAL 32-BIT (x32) LINKS IN UNIVERSAL CHIPLET INTERCONNECT EXPRESS (UCIe) 64-BIT (x64) MODULES IN PROCESSOR-BASED DEVICES > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2026/0211831 A1 - Document ID: US20260211831A1 - Status: Published application - Kind: A1 - Application number: 19/034,813 - Filed: 2025-01-23 - Published: 2026-07-23 - Earliest claimed: 2025-01-23 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Santhosh Reddy Akavaram; Sridhar Anumala; Sang Tran; Sivaiah Gopavaram; Ravindranath Doddi; Ramacharan Sundararaman - Web page: https://patentgrep.com/patent/US20260211831A1 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - G06F 13/382: {using universal interface adapter} - G06F 13/4018: {with data-width conversion} - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/4265: {on a point to point bus (G06F13/4247, G06F13/4282 take precedence)} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Providing Flexible Link Width (FLW) dual 32-bit (x32) links in Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) modules in processor-based devices is disclosed herein. In some aspects, a UCIe x64 module establishes a first x32 link with a first UCIe x32 module using mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and sideband signal lanes. The UCIe x64 module also establishes a second x32 link with a second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, redundant mainband transmit signal lanes, redundant mainband receive signal lanes, and redundant sideband signal lanes. The UCIe x64 module then establishes data transfer via the first and the second x32 links. ## Claims ### Claim 1 A processor-based device, comprising: a Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) module configured to: determine, during a first initialization of the processor-based device, that the UCIe x64 module supports Flexible Link Width (FLW); responsive to determining that the UCIe x64 module supports FLW, determine, during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe 32-bit (x32) module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively; and responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module: establish the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes; establish the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes; and establish data transfer via the first x32 link and the second x32 link. ### Claim 2 (depends on 1) The processor-based device of claim 1, wherein the UCIe x64 module is configured to determine that the UCIe x64 module supports FLW by being configured to determine that either one of a first FLW module configuration bit in a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device and a second FLW module configuration bit in a physical layer (PHY) control register of the processor-based device is set. ### Claim 3 (depends on 2) The processor-based device of claim 2, wherein the UCIe x64 module is further configured to, responsive to determining that the UCIe x64 module supports FLW, set an FLW indication of an MBINIT.PARAM message. ### Claim 4 (depends on 1) The processor-based device of claim 1, wherein the UCIe x64 module is further configured to, subsequent to determining that the first UCIe x32 module and the second UCIe x32 module require the first x32 link and the second x32 link, respectively: update a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device to indicate a count of active modules, a configuration of each active module, and a count of die-to-die stacks required to support links between the UCIe x64 module and the first and second UCIe x32 modules; and configure a first die-to-die stack and a second die-to-die stack corresponding to the first UCIe x32 module and the second UCIe x32 module, respectively. ### Claim 5 (depends on 4) The processor-based device of claim 4, wherein: the UCIe x64 module comprises a Raw Die-to-Die Interface (RDI) multiplexor configured to arbitrate data transmitted via the first and the second x32 links; and the UCIe x64 module is configured to establish the data transfer via the first x32 link and the second x32 link using the RDI multiplexor. ### Claim 6 (depends on 1) The processor-based device of claim 1, wherein the UCIe x64 module is further configured to: determine, during a second initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a single UCIe x32 module that requires a third x32 link; and responsive to determining that the UCIe x64 module is communicatively coupled to the single UCIe x32 module: establish the third x32 link with the single UCIe x32 module using the plurality of mainband transmit signal lanes including the first 32 bits of the mainband data transmit signal lane, the plurality of mainband receive signal lanes including the first 32 bits of the mainband data receive signal lane, and the plurality of sideband signal lanes; and establish data transfer via the third x32 link. ### Claim 7 (depends on 1) The processor-based device of claim 1, wherein the UCIe x64 module is further configured to: determine, during a third initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a single UCIe x64 module that requires an x64 link; and responsive to determining that the UCIe x64 module is communicatively coupled to the single UCIe x64 module: establish the x64 link with the single UCIe x64 module using the plurality of mainband transmit signal lanes including all 64 bits of the mainband data transmit signal lane, the plurality of mainband receive signal lanes including all 64 bits of the mainband data receive signal lane, the plurality of sideband signal lanes, the plurality of redundant mainband transmit signal lanes, the plurality of redundant mainband receive signal lanes, and the plurality of redundant sideband signal lanes; and establish data transfer via the x64 link. ### Claim 8 (depends on 1) The processor-based device of claim 1, integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. ### Claim 9 A processor-based device, comprising: means for determining, during a first initialization of the processor-based device, that a Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) module of the processor-based device supports Flexible Link Width (FLW); means for determining, during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe 32-bit (x32) module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively, responsive to determining that the UCIe x64 module supports FLW; means for establishing the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes, responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module; means for establishing the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes, responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module; and means for establishing data transfer via the first x32 link and the second x32 link, responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module. ### Claim 10 A method for providing Flexible Link Width (FLW) dual 32-bit (x32) links in Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) modules, comprising: determining, by a UCIe x64 module during a first initialization of a processor-based device, that the UCIe x64 module supports FLW; responsive to determining that the UCIe x64 module supports FLW, determining, by the UCIe x64 module during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe x32 module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively; and responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module: establishing, by the UCIe x64 module, the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes; establishing, by the UCIe x64 module, the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes; and establishing, by the UCIe x64 module, data transfer via the first x32 link and the second x32 link. ### Claim 11 (depends on 10) The method of claim 10, wherein determining that the UCIe x64 module supports FLW comprises determining that either one of a first FLW module configuration bit in a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device and a second FLW module configuration bit in a physical layer (PHY) control register of the processor-based device is set. ### Claim 12 (depends on 11) The method of claim 11, further comprising, responsive to determining that the UCIe x64 module supports FLW, setting, by the UCIe x64 module, an FLW indication of an MBINIT.PARAM message. ### Claim 13 (depends on 10) The method of claim 10, further comprising, subsequent to determining that the first UCIe x32 module and the second UCIe x32 module require the first x32 link and the second x32 link, respectively: updating, by the UCIe x64 module, a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device to indicate a count of active modules, a configuration of each active module, and a count of die-to-die stacks required to support links between the UCIe x64 module and the first and second UCIe x32 modules; and configuring, by the UCIe x64 module, a first die-to-die stack and a second die-to-die stack corresponding to the first UCIe x32 module and the second UCIe x32 module, respectively. ### Claim 14 (depends on 13) The method of claim 13, wherein: the UCIe x64 module comprises a Raw Die-to-Die Interface (RDI) multiplexor configured to arbitrate data transmitted via the first and the second x32 links; and establishing the data transfer via the first x32 link and the second x32 link comprises establishing data transfer using the RDI multiplexor. ### Claim 15 (depends on 10) The method of claim 10, further comprising: determining, by the UCIe x64 module during a second initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a single UCIe x32 module that requires a third x32 link; and responsive to determining that the UCIe x64 module is communicatively coupled to the single UCIe x32 module: establishing, by the UCIe x64 module, the third x32 link with the single UCIe x32 module using the plurality of mainband transmit signal lanes including the first 32 bits of the mainband data transmit signal lane, the plurality of mainband receive signal lanes including the first 32 bits of the mainband data receive signal lane, and the plurality of sideband signal lanes; and establishing, by the UCIe x64 module, data transfer via the third x32 link. ### Claim 16 (depends on 10) The method of claim 10, further comprising: determining, during a third initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a single UCIe x64 module that requires an x64 link; and responsive to determining that the UCIe x64 module is communicatively coupled to the single UCIe x64 module: establishing, by the UCIe x64 module, the x64 link with the single UCIe x64 module using the plurality of mainband transmit signal lanes including all 64 bits of the mainband data transmit signal lane, the plurality of mainband receive signal lanes including all 64 bits of the mainband data receive signal lane, the plurality of sideband signal lanes, the plurality of redundant mainband transmit signal lanes, the plurality of redundant mainband receive signal lanes, and the plurality of redundant sideband signal lanes; and establishing, by the UCIe x64 module, data transfer via the x64 link. ### Claim 17 A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device of a processor-based device, cause a Universal Chiplet Interconnect Express (UCIe) 64-bit (x64) module of the processor device to: determine, during a first initialization of the processor-based device, that the UCIe x64 module supports Flexible Link Width (FLW); responsive to determining that the UCIe x64 module supports FLW, determine, during the first initialization of the processor-based device, that the UCIe x64 module is communicatively coupled to a first UCIe 32-bit (x32) module and a second UCIe x32 module that require a first x32 link and a second x32 link, respectively; and responsive to determining that the UCIe x64 module is communicatively coupled to the first UCIe x32 module and the second UCIe x32 module: establish the first x32 link with the first UCIe x32 module using a plurality of mainband transmit signal lanes including a first 32 bits of a mainband data transmit signal lane, a plurality of mainband receive signal lanes including a first 32 bits of a mainband data receive signal lane, and a plurality of sideband signal lanes; establish the second x32 link with the second UCIe x32 module using a second 32 bits of the mainband data transmit signal lane, a second 32 bits of the mainband data receive signal lane, a plurality of redundant mainband transmit signal lanes, a plurality of redundant mainband receive signal lanes, and a plurality of redundant sideband signal lanes; and establish data transfer via the first x32 link and the second x32 link. ### Claim 18 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the computer-executable instructions cause the UCIe x64 module to determine that the UCIe x64 module supports FLW by causing the UCIe x64 module to determine that either one of a first FLW module configuration bit in a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device and a second FLW module configuration bit in a physical layer (PHY) control register of the processor-based device is set. ### Claim 19 (depends on 18) The non-transitory computer-readable medium of claim 18, wherein the computer-executable instructions further cause the UCIe x64 module to, responsive to determining that the UCIe x64 module supports FLW, set an FLW indication of an MBINIT.PARAM message. ### Claim 20 (depends on 17) The non-transitory computer-readable medium of claim 17, wherein the computer-executable instructions further cause the UCIe x64 module to, subsequent to determining that the first UCIe x32 module and the second UCIe x32 module require the first x32 link and the second x32 link, respectively: update a Device Vendor Specific Extended Capabilities (DVSEC) Link Capability register of the processor-based device to indicate a count of active modules, a configuration of each active module, and a count of die-to-die stacks required to support links between the UCIe x64 module and the first and second UCIe x32 modules; and configure a first die-to-die stack and a second die-to-die stack corresponding to the first UCIe x32 module and the second UCIe x32 module, respectively.