US 2026/0211819 A1 · BUFFER EXPANSION FOR RANDOM WRITE OPERATIONS

Abstract

Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads. Memory locations within the memory system controller are typically allocated for use during various operations. During different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. By recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the L2P address translation table data used during the write operations to retain larger portions of the L2P address translation table in the buffer.

Claims21

Dependent claims

(canceled)

A memory system, comprising:

a non-volatile memory;
and
one or more controllers comprising a volatile memory, wherein the one or more controllers are configured to cause the memory system to:
receive a plurality of write commands associated with a plurality of logical addresses;
and
allocate, for a duration based at least in part on the plurality of write commands comprising random write commands, a plurality of volatile memory cells of the volatile memory to use as a buffer for storing mapping information between the plurality of logical addresses and a plurality of physical addresses for the non-volatile memory, wherein allocating the plurality of volatile memory cells increases a size of the buffer from a first size to a second size.

3 more elements

A memory system, comprising:

a non-volatile memory;
and
one or more controllers comprising a volatile memory, wherein the one or more controllers are configured to cause the memory system to:
receive a plurality of write commands associated with a plurality of logical addresses;
and
de-allocate, based at least in part on the plurality of write commands comprising non-random write commands, a plurality of volatile memory cells of the volatile memory from use as a buffer for storing mapping information between the plurality of logical addresses and a plurality of physical addresses for the non-volatile memory, wherein de-allocating the plurality of volatile memory cells decreases a size of the buffer from a first size to a second size.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/444,015Filed 8 Jan 2026

Priority

16 Feb 2023

Published

23 Jul 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…

Family

Application63/446,085Us provisional application · filed 16 Feb 2023

Application18/431,544Continuation · filed 2 Feb 2024

Application19/444,015Continuation

US 12,541,465 B2Related patent

US 2024/0281383 A1Published application

US 2026/0211819 A1This patent

From the US filing history. Foreign family members aren’t listed.

Buffer expansion for random write operations

Life of this patent

Buffer expansion for random write operations

Life of this patent

Abstract

Claims21