Linear to physical address translation with support for page attributes

A computing system comprising:

• a host memory;
• an I/O device;
• a guest memory;
• and
• a processor comprising:
• a physical address return register,
• wherein the processor is to receive an instruction to translate a virtual address to a physical address, and
• wherein the instruction is to cause the processor to:
• translate the virtual address to the physical address using a first set of page tables;
• store the physical address in the physical address return register;
• and
• store at least one attribute associated with the physical address translated from the virtual address in the physical address return register,
• wherein the at least one attribute indicates whether the physical address resides in the host memory or the guest memory.

A system comprising:

• an application hosted on a processor, the processor associated with a host memory, the host memory associated with a host execution area;
• a kernel, executing on the processor, providing communication between the application and a hardware circuit including an address translation hardware circuit, the kernel executing at a higher privilege level than the application, the kernel executing an instruction configured to:
• receive a virtual memory address as an input parameter to the instruction;
• provide, to the address translation hardware circuit, the virtual memory address, the virtual memory address associated with a guest memory, the guest memory associated with a guest execution area, wherein the address translation hardware circuit includes operations comprising:
• receiving a memory request including the virtual memory address;
• if the virtual memory address is found in a translation lookaside buffer, providing, as output parameters from the instruction, a physical memory address and a page attribute associated with the physical memory address by determining whether a page associated with the physical memory address is present in the guest memory associated with the guest execution area, the determining based on a status in a last level of a page table mapping the virtual memory address to the physical memory address, the status of the page being determined without accessing data corresponding to the physical memory address, the status determination saving an access to a memory hierarchy associated with the physical memory address;
• and
• if the virtual memory address is not found in the translation lookaside buffer, providing, as one of the output parameters from the instruction, an indication where a page fault occurred without generating an exception.