Error reporting using link parity locations
AssigneeMicron Technology, Inc.
InventorScott E. SCHAEFER
Life of this patent
Estimating the term…
Abstract
In some implementations, a memory apparatus may obtain, from a host system, a first message comprising data and link parity information associated with the data. The memory apparatus may determine that the data includes one or more errors based on the link parity information. The memory apparatus may store a first value indicating that the data includes the one or more errors. The memory apparatus may provide, as part of a read request for the data, a second message comprising the data and a second value, the second value indicating that the data includes the one or more errors.
Claims25
A memory apparatus, comprising:
- one or more components configured to:
- obtain, from a host system, a first message comprising data and link parity information associated with the data;
- determine, by the memory apparatus, that the data includes one or more errors based on the link parity information;
- store, by the memory apparatus, a first value indicating that the data includes the one or more errors;
- and
- provide, to the host system and as part of a read request for the data, a second message comprising the data and a second value, the second value indicating that the data includes the one or more errors.
A memory apparatus, comprising:
- one or more components configured to:
- obtain, from a host system, a first message comprising data and link parity information associated with the data;
- determine, by the memory apparatus, that the data includes one or more errors based on the link parity information;
- and
- selectively, based on whether the memory apparatus is operating in a link parity feedback mode, store a first value indicating that the data includes the one or more errors to one or more fault-mode registers or store a second value indicating that the data includes the one or more errors to one or more memory arrays provisioned for parity information corresponding to the data.
A host system, comprising:
- one or more components configured to:
- provide, to a memory apparatus, a command indicating that the memory apparatus is to operate in a link parity feedback mode;
- provide, to the memory apparatus, a first message comprising data and link parity information associated with the data;
- and
- obtain, from the memory apparatus and as part of a read request for the data, a second message comprising the data and a second value, the second value indicating that the data includes one or more errors.
A system, comprising:
- a host system;
- a memory apparatus;
- a host interface between the host system and the memory apparatus;
- and
- one or more controllers configured to:
- communicate, via the host interface and to the memory apparatus, a first message comprising data and link parity information associated with the data;
- determine, by the memory apparatus, that the data includes one or more errors based on the link parity information;
- store, at the memory apparatus, a first value indicating that the data includes the one or more errors;
- and
- communicate, via the host interface and to the host system, a second message comprising the data and a second value, the second value indicating that the data includes the one or more errors.
Dependencies are inferred from the claim text.