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US 2026/0211680 A1Published application
Programmable Fabric-Based Instruction Set Architecture for a Processor
AssigneeAltera Corporation
InventorsDheeraj Subbareddy, Anshuman Thakur, Ankireddy Nalamalpu, MD Altaf Hossain
Life of this patent
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Abstract
A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Specifically, a buffer of the extension architecture may be used to load data to and store data from the programmable fabric.
Claims20
A semiconductor device comprising:
- a programmable fabric;
- and
- a processor comprising:
- extension architecture that embeds the programmable fabric in the processor and comprises a register used to exchange data between the programmable fabric and the processor and to convert data between formats in the programmable fabric for consumption in a fused-multiply-add of the extension architecture;
- a decode unit to decode instructions for the processor and the programmable fabric;
- and
- an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
- receiving a microcode update with a configuration bitstream that, when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions;
- validating the microcode update;
- storing the configuration bitstream to the programmable fabric;
- causing the programmable fabric to load a corresponding configuration in the programmable fabric;
- and
- causing the programmable fabric to perform the one or more functions during operation of the processor.
10 more elements
A processor, comprising:
- a programmable fabric;
- extension architecture that embeds the programmable fabric in the processor and comprises a register used to exchange data between the programmable fabric and a remainder of the processor and to convert data between formats in the programmable fabric for consumption in a fused-multiply-add of the extension architecture;
- a decode unit to decode instructions for the processor and for the programmable fabric;
- and
- an execution unit coupled with the decode unit, wherein the execution unit, in response to the instructions, performs operations comprising:
- receiving a microcode update with a configuration bitstream that, when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions;
- validating the microcode update;
- storing the configuration bitstream to the programmable fabric;
- causing the programmable fabric to load a corresponding configuration in the programmable fabric;
- and
- causing the programmable fabric to perform the one or more functions during operation of the processor.
8 more elements
A processor comprising:
- extension architecture that embeds a programmable fabric in the processor and comprises a register used to exchange data between the programmable fabric and the processor and to convert data between formats in the programmable fabric for consumption in a fused-multiply-add of the extension architecture;
- and
- an execution unit performs operations comprising:
- receiving a microcode update with a configuration bitstream that, when loaded into the programmable fabric, configures the programmable fabric to perform one or more functions;
- validating the microcode update;
- storing the configuration bitstream to the programmable fabric;
- causing the programmable fabric to load a corresponding configuration in the programmable fabric;
- and
- causing the programmable fabric to perform the one or more functions during operation of the processor.
6 more elements
Dependencies are inferred from the claim text.